Datasheet

Section 10 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Sep. 28, 2009 Page 200 of 710
REJ09B0384-0300
10.2.7 Timer Output Compare Control Register (TOCR)
TOCR enables output from the output compare pins, selects the output levels, switches access
between output compare registers A and B, and controls the OCRA operating modes.
Bit Bit Name
Initial
Value
R/W Description
7 ⎯ 0 R Reserved
This bit is always read as 0 and cannot be modified.
6 OCRAMS 0 R/W Output Compare A Mode Select
Specifies whether OCRA is used in the normal operating
mode or in the operating mode using OCRAR and
OCRAF.
0: The normal operating mode is specified for OCRA
1: The operating mode using OCRAR and OCRAF is
specified for OCRA
5 ICRS 0 R/W Input Capture Register Select
Controls the access to OCRAR and OCRAF.
0: Access is disabled.
1: Access is enabled.
4 OCRS 0 R/W Output Compare Register Select
OCRA and OCRB share the same address. When this
address is accessed, the OCRS bit selects which register
is accessed. The operation of OCRA or OCRB is not
affected.
0: OCRA is selected
1: OCRB is selected
3 to 0 ⎯ All 0 R Reserved
These bits are always read as 0 and cannot be modified.