Datasheet

Section 10 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Sep. 28, 2009 Page 199 of 710
REJ09B0384-0300
10.2.6 Timer Control Register (TCR)
TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer
mode, and selects the FRC clock source.
Bit Bit Name
Initial
Value
R/W Description
7 to 2 ⎯ All 0 R Reserved
These bits are always read as 0 and cannot be modified.
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select 1 and 0
Select clock source for FRC.
00: φ/2 internal clock source
01: φ/8 internal clock source
10: φ/32 internal clock source
11: Reserved