Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxi of xxxiv
REJ09B0384-0300
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram ............................................................................................ 3
Figure 1.2 Pin Assignment (BP-112) ......................................................................................... 4
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode) ................................................................ 17
Figure 2.2 Stack Structure in Normal Mode ............................................................................ 17
Figure 2.3 Exception Vector Table (Advanced Mode) ............................................................ 18
Figure 2.4 Stack Structure in Advanced Mode ........................................................................ 19
Figure 2.5 Memory Map .......................................................................................................... 20
Figure 2.6 CPU Registers......................................................................................................... 21
Figure 2.7 Usage of General Registers..................................................................................... 22
Figure 2.8 Stack ....................................................................................................................... 23
Figure 2.9 General Register Data Formats (1) ......................................................................... 26
Figure 2.9 General Register Data Formats (2) ......................................................................... 27
Figure 2.10 Memory Data Formats............................................................................................ 28
Figure 2.11 Instruction Formats (Examples).............................................................................. 40
Figure 2.12 Branch Address Specification in Memory Indirect Mode ...................................... 44
Figure 2.13 State Transitions ..................................................................................................... 48
Section 3 MCU Operating Modes
Figure 3.1 Address Map........................................................................................................... 56
Section 4 Exception Handling
Figure 4.1 Reset Sequence .......................................................................................................61
Figure 4.2 Stack Status after Exception Handling.................................................................... 63
Figure 4.3 Operation When SP Value is Odd .......................................................................... 64
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller ................................................................... 66
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 ......................................................... 75
Figure 5.3 Block Diagram of Interrupt Control Operation....................................................... 78
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance
in Interrupt Control Mode 0.................................................................................... 81
Figure 5.5 State Transition in Interrupt Control Mode 1.......................................................... 82