Datasheet

Section 9 14-Bit PWM Timer (PWMX)
Rev. 3.00 Sep. 28, 2009 Page 189 of 710
REJ09B0384-0300
t
f1
t
f2
t
f255
t
f256
t
H1
t
H2
t
H3
t
H255
t
H256
1 conversion cycle
t
f1
= t
f2
= t
f3
= ··· = t
f255
= t
f256
= T× 64
t
H1
+ t
H2
+ t
H3
+ ··· + t
H255
+ t
H256
= T
H
t
f1
t
f2
t
f63
t
f64
t
H1
t
H2
t
H3
t
H63
t
H64
1 conversion cycle
t
f1
= t
f2
= t
f3
= ··· = t
f63
= t
f64
= T× 256
t
H1
+ t
H2
+ t
H3
+ ··· + t
H63
+ t
H64
= T
H
a. CFS = 0 [base cycle = resolution (T) × 64]
b. CFS = 1 [base cycle = resolution (T) × 256]
Figure 9.4 Output Waveform (OS = 1, DADR corresponds to T
H
)
An example of the additional pulses when CFS = 1 (base cycle = resolution (T) × 256) and OS = 1
(inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in
DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0)
determine the locations of the additional pulses as shown in figure 9.5.
Table 9.4 lists the locations of the additional pulses.
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS
11
Duty cycle of base pulse Location of additional pulses
Figure 9.5 D/A Data Register Configuration when CFS = 1
In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in
figure 9.6. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of
the base pulse duty cycle is 2/256 × (T).