Datasheet

Section 9 14-Bit PWM Timer (PWMX)
Rev. 3.00 Sep. 28, 2009 Page 187 of 710
REJ09B0384-0300
PCSR Fixed DADR Bits
PWCKX0
PWCKX1
Bit Data
C B A
CKS
Reso-
lution
T
(μs)
CFS
Base
Cycle
Conver-
sion
Cycle
TL/TH
(OS = 0/OS = 1)
Accuracy
(Bits)
DA3 DA2 DA1 DA0
Conversion
Cycle*
0 1 1 1 10.24 0 14 167.77 ms
12 0 0 41.94 ms
655.4 μs/
1.5 kHz
167.77 ms Always low/high output
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
10 0 0 0 0 10.49 ms
1 14 167.77 ms
12 0 0 41.94 ms
(φ/256)
2621.4 μs/
0.4 kHz
167.77 ms Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
10 0 0 0 0 10.49 ms
1 0 0 1 40.96 0 14 671.09 ms
12 0 0 167.77 ms
2.62 ms/
381.5 Hz
671.09 ms Always low/high output
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
10 0 0 0 0 41.94 ms
1 14 671.09 ms
12 0 0 167.77 ms
(φ/1024)
10.49 ms/
95.4 Hz
671.09 ms Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
10 0 0 0 0 41.94 ms
1 0 1 1 163.84 0 14 2.684 s
12 0 0 0.671 s
10.49 ms/
95.4 Hz
2.684 s Always low/high output
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
10 0 0 0 0 0.168 s
1 14 2.684 s
12 0 0 0.671 s
(φ/4096)
41.94 ms/
23.8 Hz
2.684 s Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
10 0 0 0 0 0.168 s
1 1 0 1 655.36 0 14 10.737 s
12 0 0 2.684 s
41.94 ms/
23.8 Hz
10.737 s Always low/high output
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
10 0 0 0 0 0.671 s
1 14 10.737 s
12 0 0 2.684 s
(φ/16384)
167.77 ms/
6.0 Hz
10.737 s Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
10 0 0 0 0 0.671 s
1 1 1 1 Setting
prohibited
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Note: * Indicates the conversion cycle when specific DA3 to DA0 bits are fixed.