Datasheet

Section 9 14-Bit PWM Timer (PWMX)
Rev. 3.00 Sep. 28, 2009 Page 178 of 710
REJ09B0384-0300
9.2 Input/Output Pins
Table 9.1 lists the PWMX (D/A) module input and output pins.
Table 9.1 Pin Configuration
Name Abbreviation I/O Function
PWMX output pin 0 PWX0 Output PWM timer pulse output of PWMX_0 channel A
PWMX output pin 1 PWX1 Output PWM timer pulse output of PWMX_0 channel B
PWMX output pin 2 PWX2 Output PWM timer pulse output of PWMX_1 channel A
PWMX output pin 3 PWX3 Output PWM timer pulse output of PWMX_1 channel B
9.3 Register Descriptions
The PWMX (D/A) module has the following registers. For details on the module stop control
register, see section 22.1.3, Module Stop Control Registers H, L, and A (MSTPCRH, MSTPCRL,
MSTPCRA).
• PWMX (D/A) counter (DACNT)
• PWMX (D/A) data register A (DADRA)
• PWMX (D/A) data register B (DADRB)
• PWMX (D/A) control register (DACR)
• Peripheral clock select register (PCSR)
Note: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT.
Switching is performed by the REGS bit in DACNT or DADRB.