Datasheet

Rev. 3.00 Sep. 28, 2009 Page xix of xxxiv
REJ09B0384-0300
20.3.4 ID Code Register (SDIDR)................................................................................... 616
20.4 Operation ........................................................................................................................... 617
20.4.1 TAP Controller State Transitions.......................................................................... 617
20.4.2 JTAG Reset........................................................................................................... 618
20.5 Boundary Scan................................................................................................................... 618
20.5.1 Supported Instructions .......................................................................................... 618
20.6 Usage Notes ....................................................................................................................... 621
Section 21 Clock Pulse Generator .....................................................................625
21.1 Oscillator............................................................................................................................ 626
21.1.1 Connecting Crystal Resonator .............................................................................. 626
21.1.2 External Clock Input Method................................................................................ 627
21.2 PLL Multiplier Circuit ....................................................................................................... 628
21.3 Medium-Speed Clock Divider ........................................................................................... 628
21.4 Bus Master Clock Select Circuit........................................................................................ 628
21.5 Subclock Input Circuit ....................................................................................................... 628
21.6 Subclock Waveform Shaping Circuit................................................................................. 628
21.7 Clock Select Circuit ........................................................................................................... 629
21.8 Usage Notes ....................................................................................................................... 629
21.8.1 Note on Resonator ................................................................................................ 629
21.8.2 Notes on Board Design ......................................................................................... 629
21.8.3 Note on Operation Check...................................................................................... 630
Section 22 Power-Down Modes ........................................................................631
22.1 Register Descriptions ......................................................................................................... 632
22.1.1 Standby Control Register (SBYCR) ..................................................................... 632
22.1.2 Low-Power Control Register (LPWRCR) ............................................................ 635
22.1.3 Module Stop Control Registers H, L, and A
(MSTPCRH, MSTPCRL, MSTPCRA)................................................................. 636
22.1.4 Sub-Chip Module Stop Control Registers BH, BL
(SUBMSTPBH, SUBMSTPBL)........................................................................... 638
22.2 Mode Transitions and LSI States ....................................................................................... 639
22.3 Medium-Speed Mode......................................................................................................... 641
22.4 Sleep Mode ........................................................................................................................ 642
22.5 Software Standby Mode..................................................................................................... 643
22.6 Hardware Standby Mode ................................................................................................... 645
22.7 Module Stop Mode ............................................................................................................ 646
22.8 Usage Notes ....................................................................................................................... 647
22.8.1 I/O Port Status....................................................................................................... 647
22.8.2 Current Consumption when Waiting for Oscillation Settling............................... 647