Datasheet
Section 8 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 173 of 710
REJ09B0384-0300
• PE4/LFRAME
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE4DDR bit.
LPC Disabled Enabled
PE4DDR 0 1 x
Pin function PE4 input pin PE4 output pin LFRAME input pin
[Legend]
x: Don't care
• PE3/LAD3
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE3DDR bit.
LPC Disabled Enabled
PE3DDR 0 1 x
Pin function PE3 input pin PE3 output pin LAD3 input/output pin
[Legend]
x: Don't care
• PE2/LAD2
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE2DDR bit.
LPC Disabled Enabled
PE2DDR 0 1 x
Pin function PE2 input pin PE2 output pin LAD2 input/output pin
[Legend]
x: Don't care