Datasheet

Rev. 3.00 Sep. 28, 2009 Page xvii of xxxiv
REJ09B0384-0300
16.3.21 BT Status Register 0 (BTSR0).............................................................................. 451
16.3.22 BT Status Register 1 (BTSR1).............................................................................. 454
16.3.23 BT Control Status Register 0 (BTCSR0) .............................................................. 457
16.3.24 BT Control Status Register 1 (BTCSR1) .............................................................. 458
16.3.25 BT Control Register (BTCR)................................................................................ 460
16.3.26 BT Data Buffer (BTDTR)..................................................................................... 463
16.3.27 BT Interrupt Mask Register (BTIMSR)................................................................ 463
16.3.28 BT FIFO Valid Size Register 0 (BTFVSR0) ........................................................ 465
16.3.29 BT FIFO Valid Size Register 1 (BTFVSR1) ........................................................ 465
16.4 Operation ........................................................................................................................... 466
16.4.1 LPC interface Activation ...................................................................................... 466
16.4.2 LPC I/O Cycles..................................................................................................... 466
16.4.3 SMIC Mode Transfer Flow................................................................................... 468
16.4.4 BT Mode Transfer Flow ....................................................................................... 471
16.4.5 LPC Interface Shutdown Function........................................................................ 473
16.4.6 LPC Interface Serialized Interrupt Operation (SERIRQ)...................................... 476
16.5 Interrupt Sources................................................................................................................ 479
16.5.1 IBFI1, IBFI2, IBFI3, and ERRI ............................................................................ 479
16.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9,
HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15............................ 480
16.6 Usage Note......................................................................................................................... 483
16.6.1 Data Conflict......................................................................................................... 483
Section 17 A/D Converter..................................................................................485
17.1 Features.............................................................................................................................. 485
17.2 Input/Output Pins............................................................................................................... 487
17.3 Register Descriptions ......................................................................................................... 488
17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 489
17.3.2 A/D Control/Status Register (ADCSR) ................................................................ 490
17.3.3 A/D Control Register (ADCR) ............................................................................. 492
17.4 Operation ........................................................................................................................... 493
17.4.1 Single Mode.......................................................................................................... 493
17.4.2 Scan Mode ............................................................................................................ 494
17.4.3 Input Sampling and A/D Conversion Time .......................................................... 496
17.4.4 Timing of External Trigger Input.......................................................................... 499
17.5 Interrupt Source ................................................................................................................. 499
17.6 A/D Conversion Accuracy Definitions .............................................................................. 500
17.7 Usage Notes ....................................................................................................................... 502
17.7.1 Setting of Module Stop Mode............................................................................... 502
17.7.2 Permissible Signal Source Impedance .................................................................. 502