Datasheet

Section 8 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 141 of 710
REJ09B0384-0300
P4n input
1 expected
P4nDR
0 expected
P4nDR
(n = 7 to 4)
Figure 8.4 Noise Canceler Operation
8.4.7 Pin Functions
The relationship between register setting values and pin functions are as follows.
• P47 to P44
The pin function is switched as shown below according to the P4nDDR bit and P4nNCE bit.
When the ISSn bit in ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is
set to 1, this pin can be used as the IRQn input pin. To use this pin as the IRQn input pin, clear the
P4nDDR bit to 0.
P4nDDR 0 1
P4nNCE 0 1 x
P4n input pin DBn input Pin function
IRQn input pin IRQn input pin
(with the noise canceler)
P4n output pin
[Legend]
n = 7 to 4
x: Don't care