Datasheet

Section 8 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 140 of 710
REJ09B0384-0300
8.4.6 Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycles of the noise cancelers.
Bit Bit Name Initial Value R/W Description
7 to 3 ⎯ Undefined R/W Reserved
The read value is undefined.
2
1
0
NCCK2
NCCK1
NCCK0
0
0
0
R/W
R/W
R/W
These bits set the sampling cycle of the noise
cancelers.
• When φ = 25 MHz
000: 80 ns φ/2
001: 1.28 μs φ/32
010: 20.48 μs φ/512
011: 327.7 μs φ/8192
100: 1.31 ms φ/32768
101: 2.62 ms φ/65536
110: 5.24 ms φ/131072
111: 10.49 ms φ/262144
Latch
Pin input
Sampling clock selection
Sampling clock
Matching
detection
circuit
Port data
register
Latch
Latch
φ/2, φ/32, φ/512, φ/8192,
φ/32768, φ/65536,
φ/131072, φ/262144
Δt
Figure 8.3 Noise Canceler Circuit