Datasheet

Section 8 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 134 of 710
REJ09B0384-0300
8.3.4 Noise Canceler Enable Register (P3NCE)
P3NCE enables or disables the noise canceler circuit at port 3.
Bit Bit Name Initial Value R/W Description
7 P37NCE 0 R/W
6 P36NCE 0 R/W
5 P35NCE 0 R/W
4 P34NCE 0 R/W
3 P33NCE 0 R/W
2 P32NCE 0 R/W
1 P31NCE 0 R/W
When the noise canceler circuit is enabled, the pin state
is fetched in the P3DR in the sampling cycle set by the
NCCS.
The operating state changes according to the other
control bits. Check the pin functions.
0 P30NCE 0 R/W
8.3.5 Noise Canceler Mode Control Register (P3NCMC)
P3NCMC controls whether 1 or 0 is expected for the input signal to port 3 in bit units.
Bit Bit Name Initial Value R/W Description
7 P37NCMC 1 R/W
6 P36NCMC 1 R/W
5 P35NCMC 1 R/W
4 P34NCMC 1 R/W
3 P33NCMC 1 R/W
2 P32NCMC 1 R/W
1 P31NCMC 1 R/W
1 expected: 1 is stored in the port data register while 1
is input stably
0 expected: 0 is stored in the port data register while 0
is input stably
0 P30NCMC 1 R/W