Datasheet

Section 8 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 125 of 710
REJ09B0384-0300
Section 8 I/O Ports
Table 8.1 is a summary of the port functions. The pins of each port also function as input/output
pins of peripheral modules and interrupt input pins. Each input/output port includes a data
direction register (DDR) that controls input/output and a data register (DR) that stores output data.
DDR and DR are not provided for an input-only port.
Ports 1 to 4, 6, and A have built-in input pull-up MOSs. For port A, the on/off status of the input
pull-up MOS is controlled by DDR and ODR. Ports 1 to 4, and 6 have an input pull-up MOS
control register (PCR), in addition to DDR and DR, to control the on/off status of the input pull-up
MOSs.
Port 3 pins and pins 47 to 44 have built-in de-bouncers (DBn) that eliminate noises in the input
signals.
Port 4 are designed for retain state outputs (RSn), which retain the output values on the pins even
if a reset is generated when watchdog timer has overflowed.
Ports 1 to 6, and 8 to E can drive a single TTL load and 30 pF capacitive load. All the I/O ports
can drive a Darlington transistor in output mode. Ports 8, and C0 to C3 are NMOS push-pull
output.
Table 8.1 Port Functions
Port Description Single-Chip Mode I/O Status
Port 1 General I/O port P17
P16
P15
P14
P13
P12
P11
P10
Built-in input
pull-up MOS
Port 2 General I/O port P23
P22
P21
P20
Built-in input
pull-up MOS