Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Sep. 28, 2009 Page 119 of 710
REJ09B0384-0300
Table 7.8 DTC Execution Status
Mode
Vector Read
I
Register
Information
Read/Write
J
Data Read
K
Data Write
L
Internal
Operations
M
Normal transfer 1 6 1 1 3
Repeat transfer 1 6 1 1 3
Block transfer 1 6 N N 3
[Legend]
N: Block size (initial setting of CRAH and CRAL)
Table 7.9 Number of States Required for Each Execution Status
Object to be Accessed
On-Chip RAM
(H'FFEC00 to
H'FFEFFF)
On-Chip RAM
(On-chip RAM area
other than H'FFEC00
to H'FFEFFF)
On-Chip
ROM
On-Chip I/O
Registers
Bus width
32 16 16 8 16
Access states 1 1 1 2 2
Vector read S
I
⎯ ⎯ 1 ⎯ ⎯ Execution
status
Register information
read/write S
J
1 ⎯ ⎯ ⎯ ⎯
Byte data read S
K
1 1 1 2 2
Word data read
S
K
1 1 1 4 2
Byte data write 1 1 1 2 2
Word data write
S
L
1 1 1 4 2
Internal operation
S
M
1 1 1 1 1
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S
I
+ Σ (J · S
J
+ K · S
K
+ L · S
L
) + M · S
M
For example, when the DTC vector address table is located in on-chip ROM, normal transfer
mode is set, and data is transferred from on-chip ROM to an internal I/O register, then the time