Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Sep. 28, 2009 Page 112 of 710
REJ09B0384-0300
7.6 Operation
The DTC stores register information in on-chip RAM. When activated, the DTC reads register
information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated
register information back to on-chip RAM. The pre-storage of register information in memory
makes it possible to transfer data over any required number of channels. The transfer mode can be
specified as normal transfer mode, repeat transfer mode, or block transfer mode. Setting the
CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation
source (chain transfer).
The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed depending on its register information.
Start
End
Read DTC vector
Read register information
Data transfer
Write register information
Clear an activation flag
Interrupt exception
handling
Clear DTCER
CHNE = 1
Next transfer
Yes
Yes
No
Transfer counter = 0
or DISEL = 1
No
Figure 7.5 DTC Operation Flowchart