Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Sep. 28, 2009 Page 110 of 710
REJ09B0384-0300
7.5 Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFEC00 to H'FFEFFF).
Register information should be located at an address that is a multiple of four within the range.
The method for locating the register information in address space is shown in figure 7.3. Locate
MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 7.3, and the register information start address should be located at the
vector address corresponding to the interrupt source in the DTC vector table. The DTC reads the
start address of the register information from the vector table set for each activation source, and
then reads the register information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.
The configuration of the vector address is a 2-byte unit. Specify the lower two bytes of the register
information start address.
MRA
0123
SAR
MRB
DAR
CRA
CRB
MRA
SAR
MRB
DAR
CRA
CRB
Lower address
4 bytes
Register information
Register information
for 2nd transfer in
chain transfer
Register
information
start address
Chain
transfer
Figure 7.3 DTC Register Information Location in Address Space