Datasheet

Section 7 Data Transfer Controller (DTC)

Rev. 3.00 Sep. 28, 2009 Page 107 of 710

REJ09B0384-0300

7.3 DTC Event Counter

To count events of EVENT 0 to EVENT7 by the DTC event counter function, set DTC as below.

Table 7.2 DTC Event Counter Conditions

MRA 7, 6 SM1, SM0 00: SAR is fixed.

5, 4 DM1, DM0 00: DAR is fixed.

3, 2 MD1, MD0 01: Repeat transfer mode

1 DTS 0: Destination is repeat area

0 Sz 1: Word size transfer

MRB 7 CHNE 0: Chain transfer is disabled

6 DISEL 0: Interrupt request is generated when data is transferred by

the number of specified times

5 to 0 ⎯ B'000000

SAR 23 to 0 ⎯

DAR 23 to 0 ⎯

Identical optional RAM address. Its lower five bits are B'00000.

The start address of 16 words is this address. They are

incremented every time an event is detected in EVENT0 to

EVENT15.

CRAH 7 to 0 ⎯ H'FF

CRAL 7 to 0 ⎯ H'FF

CRBH 7 to 0 ⎯ H'FF

CRBL 7 to 0 ⎯ H'FF

DTCERC 4 DTCEC4 1: DTC function of the event counter is enabled

KBCOMP 7 EVENTE 1: Event counter enable

RAM ⎯ ⎯ (SAR, DAR) : Result of EVENT0 count

(SAR, DAR) + 2: Result of EVENT 1 count

(SAR, DAR) + 4: Result of EVENT 2 count

↓

(SAR, DAR) + 14: Result of EVENT 7 count

The corresponding flag to ECS input pin is set to 1 when the event pins that are specified by the

ECSB2 to ECSB0 in ECCR detect the edge events specified by the EDSB in ECCR. For this flag

state, status/address codes are generated.

An EVENTI interrupt request is generated even if only one bit in ECS is set to 1.