Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Sep. 28, 2009 Page 106 of 710
REJ09B0384-0300
Bit Bit Name
Initial
Value
R/W Description
2 to 0 ECSB2 to
ECSB0
All 0 R/W Event Counter Channel Select 2 to 0
These bits select pins for event counter input. A series
of pins are selected starting from EVENT0. When
PAnDDR is set to 1, inputting events to EVENT0 to
EVENT7 is ignored.
000: EVENT0 is used
001: EVENT0 to EVENT1 are used
010: EVENT0 to EVENT2 are used
011: EVENT0 to EVENT3 are used
100: EVENT0 to EVENT4 are used
101: EVENT0 to EVENT5 are used
110: EVENT0 to EVENT6 are used
111: EVENT0 to EVENT7 are used
7.2.11 Event Counter Status Register (ECS)
ECS is a 16-bit register that holds events temporarily. The DTC decides the counter to be
incremented according to the state of this register. Reading this register allows the monitoring of
events that are not yet counted by the event counter. Access in 8-bit unit is not allowed.
Bit Bit Name
Initial
Value
R/W Description
15 to 8 ⎯ All 0 R Reserved
7 to 0 E7 to E0 0 R Event Monitor 7 to 0
These bits indicate processed/unprocessed states of
the events that are input to EVENT7 to EVENT0.
0: The corresponding event is already processed
1: The corresponding event is not yet processed