Datasheet

Rev. 3.00 Sep. 28, 2009 Page xii of xxxiv
REJ09B0384-0300
8.11.2 Port E Output Data Register (PEODR)................................................................. 171
8.11.3 Port E Input Data Register (PEPIN) ..................................................................... 171
8.11.4 Pin Functions ........................................................................................................ 172
8.12 Change of Peripheral Function Pins................................................................................... 175
8.12.1 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register
(ISSR) ................................................................................................................... 175
Section 9 14-Bit PWM Timer (PWMX) .........................................................177
9.1 Features.............................................................................................................................. 177
9.2 Input/Output Pins............................................................................................................... 178
9.3 Register Descriptions ......................................................................................................... 178
9.3.1 PWMX (D/A) Counter (DACNT) ........................................................................ 179
9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB).......................... 180
9.3.3 PWMX (D/A) Control Register (DACR) ............................................................. 182
9.3.4 Peripheral Clock Select Register (PCSR) ............................................................. 183
9.4 Bus Master Interface.......................................................................................................... 184
9.5 Operation ........................................................................................................................... 185
Section 10 16-Bit Free-Running Timer (FRT)..................................................193
10.1 Features.............................................................................................................................. 193
10.2 Register Descriptions......................................................................................................... 195
10.2.1 Free-Running Counter (FRC) ............................................................................... 195
10.2.2 Output Compare Registers A and B (OCRA and OCRB) .................................... 195
10.2.3 Output Compare Registers AR and AF (OCRAR and OCRAF) .......................... 196
10.2.4 Timer Interrupt Enable Register (TIER)............................................................... 197
10.2.5 Timer Control/Status Register (TCSR)................................................................. 198
10.2.6 Timer Control Register (TCR).............................................................................. 199
10.2.7 Timer Output Compare Control Register (TOCR) ............................................... 200
10.3 Operation Timing............................................................................................................... 201
10.3.1 FRC Increment Timing......................................................................................... 201
10.3.2 Output Compare Output Timing........................................................................... 201
10.3.3 FRC Clear Timing ................................................................................................ 202
10.3.4 Timing of Output Compare Flag (OCF) Setting................................................... 202
10.3.5 Timing of FRC Overflow Flag (OVF) Setting...................................................... 203
10.3.6 Automatic Addition Timing.................................................................................. 204
10.4 Interrupt Sources................................................................................................................ 204
10.5 Usage Notes ....................................................................................................................... 205
10.5.1 Conflict between FRC Write and Clear ................................................................ 205
10.5.2 Conflict between FRC Write and Increment......................................................... 206
10.5.3 Conflict between OCR Write and Compare-Match .............................................. 207