Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Sep. 28, 2009 Page 103 of 710
REJ09B0384-0300
7.2.7 DTC Enable Registers (DTCER)
DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers:
DTCERA to DTCERE. The correspondence between interrupt sources and DTCE bits is shown in
tables 7.1 and 7.4. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR. Multiple DTC activation sources can be set at one time (only at the initial setting) by
masking all interrupts and writing data after executing a dummy read on the relevant register.
Bit Bit Name
Initial
Value
R/W Description
7 to 0 DTCE7 to
DTCE0
All 0 R/W DTC Activation Enable
Setting this bit to 1 specifies a relevant interrupt source
as a DTC activation source.
[Clearing conditions]
When data transfer has ended with the DISEL bit in
MRB set to 1
When the specified number of transfers have ended
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not been
completed
Table 7.1 Correspondence between Interrupt Sources and DTCER
Register
Bit Bit Name DTCERA DTCERB DTCERC DTCERD DTCERE
7 DTCEn7 (16)IRQ0 (86)TXI1
6 DTCEn6 (17)IRQ1 (76)IICI2
5 DTCEn5 (18)IRQ2 (94)IICI0
4 DTCEn4 (19)IRQ3 (29)EVENTI (78)IICI3
3 DTCEn3 (28)ADI (98)IICI1 (104)ERR1
2 DTCEn2 (81)RXI3 (105)IBFI1
1 DTCEn1 (82)TXI3 (106)IBFI2
0 DTCEn0 (85)RXI1 (107)IBFI3
[Legend]
n: A to E
( ): Vector number
: Reserved. The write value should always be 0.