Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Sep. 28, 2009 Page 101 of 710
REJ09B0384-0300
7.2.2 DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit Bit Name
Initial
Value
R/W Description
7 CHNE Undefined ⎯ DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, see section 7.6.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of data transfers,
clearing of the interrupt source flag, and clearing of
DTCER are not performed.
6 DISEL Undefined ⎯ DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time data transfer ends. When this bit
is cleared to 0, a CPU interrupt request is generated
only when the specified number of data transfer ends.
5 to 0 ⎯ Undefined ⎯ Reserved
These bits have no effect on DTC operation. The write
value should always be 0.
7.2.3 DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
7.2.4 DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.