Datasheet

Rev. 3.00 Sep. 28, 2009 Page x of xxxiv
REJ09B0384-0300
7.4 Activation Sources............................................................................................................. 109
7.5 Location of Register Information and DTC Vector Table ................................................. 110
7.6 Operation ........................................................................................................................... 112
7.6.1 Normal Transfer Mode ......................................................................................... 113
7.6.2 Repeat Transfer Mode .......................................................................................... 114
7.6.3 Block Transfer Mode............................................................................................ 115
7.6.4 Chain Transfer ...................................................................................................... 116
7.6.5 Interrupt Sources................................................................................................... 117
7.6.6 Operation Timing.................................................................................................. 117
7.6.7 Number of DTC Execution States ........................................................................ 118
7.7 Procedures for Using DTC................................................................................................. 120
7.7.1 Activation by Interrupt.......................................................................................... 120
7.7.2 Activation by Software ......................................................................................... 120
7.8 Examples of Use of the DTC............................................................................................. 121
7.8.1 Normal Transfer Mode ......................................................................................... 121
7.8.2 Software Activation .............................................................................................. 122
7.9 Usage Notes ....................................................................................................................... 123
7.9.1 Module Stop Mode Setting ................................................................................... 123
7.9.2 On-Chip RAM ...................................................................................................... 123
7.9.3 DTCE Bit Setting.................................................................................................. 123
7.9.4 DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter .................. 123
Section 8 I/O Ports...........................................................................................125
8.1 Port 1.................................................................................................................................. 128
8.1.1 Port 1 Data Direction Register (P1DDR).............................................................. 128
8.1.2 Port 1 Data Register (P1DR)................................................................................. 128
8.1.3 Port 1 Pull-Up MOS Control Register (P1PCR)................................................... 129
8.1.4 Port 1 Input Pull-Up MOS .................................................................................... 129
8.2 Port 2.................................................................................................................................. 130
8.2.1 Port 2 Data Direction Register (P2DDR).............................................................. 130
8.2.2 Port 2 Data Register (P2DR)................................................................................. 130
8.2.3 Port 2 Pull-Up MOS Control Register (P2PCR)................................................... 131
8.2.4 Port 2 Input Pull-Up MOS .................................................................................... 131
8.3 Port 3.................................................................................................................................. 132
8.3.1 Port 3 Data Direction Register (P3DDR).............................................................. 132
8.3.2 Port 3 Data Register (P3DR)................................................................................. 133
8.3.3 Port 3 Pull-Up MOS Control Register (P3PCR)................................................... 133
8.3.4 Noise Canceler Enable Register (P3NCE)............................................................ 134
8.3.5 Noise Canceler Mode Control Register (P3NCMC)............................................. 134
8.3.6 Noise Canceler Cycle Setting Register (NCCS) ................................................... 135