Datasheet

Section 5 Interrupt Controller

Rev. 3.00 Sep. 28, 2009 Page 82 of 710

REJ09B0384-0300

5.6.2 Interrupt Control Mode 1

In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral

module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting.

• An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared

to 0. When the I bit is set to 1, the interrupt request is held pending.

The EVENTI interrupt is enabled or disabled by the I bit.

• An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is

cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending.

For instance, the state when the interrupt enable bit corresponding to each interrupt is set to 1, and

ICRA to ICRD are set to H'20, H'00, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts are

set to interrupt control level 1, and other interrupts are set to interrupt control level 0) is shown

below. Figure 5.6 shows a state transition diagram.

• All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > IRQ0 >

IRQ1 > address break …)

• Only NMI, IRQ2, IRQ3, and address break interrupt requests are accepted when I = 1 and UI =

• Only NMI and address break interrupt requests are accepted when I = 1 and UI = 1.

Only NMI and address break

interrupt requests are accepted

All interrupt requests

are accepted

Exception handling execution

or I 1, UI 1

I 0

I 1, UI 0

I 0UI 0

Exception handling

execution or UI 1

Only NMI, address break, and

interrupt control level 1 interrupt

requests are accepted

Figure 5.5 State Transition in Interrupt Control Mode 1