Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 79 of 710
REJ09B0384-0300
Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1,
interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in
CCR and ICR (control level).
Table 5.5 shows the interrupts selected in each interrupt control mode.
Table 5.5 Interrupts Selected in Each Interrupt Control Mode
Interrupt Mask Bits
Interrupt Control Mode I UI Selected Interrupts
0 0 x All interrupts (interrupt control level 1 has
priority)
1 x NMI and address break interrupts
1 0 x All interrupts (interrupt control level 1 has
priority)
1 0 NMI, address break, and interrupt control level 1
interrupts
1 NMI and address break interrupts
[Legend]
x: Don't care
Default Priority Determination: The priority is determined for the selected interrupt, and a
vector number is generated.
If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.6 shows operations and control signal functions in each interrupt control mode.