Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 76 of 710
REJ09B0384-0300
5.5 Interrupt Exception Handling Vector Table
Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For
default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt
requests from modules that are set to interrupt control level 1 (priority) by the ICR bit setting are
given priority and processed before interrupt requests from modules that are set to interrupt
control level 0 (no priority).
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector Address Origin of
Interrupt
Source Name
Vector
Number Advanced Mode ICR Priority
NMI 7 H'00001C ⎯ High External pin
IRQ0 16 H
'000040 ICRA7
IRQ1 17 H'000044 ICRA6
IRQ2
IRQ3
18
19
H'000048
H
'00004C
ICRA5
IRQ4
IRQ5
20
21
H'000050
H
'000054
ICRA4
IRQ6
IRQ7
22
23
H'000058
H
'00005C
ICRA3
DTC SWDTEND (Software activation
data transfer end)
24 H'000060 ICRA2
WDT_0 WOVI0 (Interval timer) 25 H'000064 ICRA1
WDT_1 WOVI1 (Interval timer) 26 H'000068 ICRA0
⎯ Address break 27 H'00006C ⎯
A/D converter ADI (A/D conversion end) 28 H'000070 ICRB7
EVC EVENTI 29 H'000074 ⎯
TMR_X CMIAX (Compare match A)
CMIBX (Compare match B)
OVIX (Overflow)
44
45
46
H'0000B0
H
'0000B4
H
'0000B8
ICRB4
FRT OCIA (Output compare A)
OCIB (Output compare B)
FOVI (Overflow)
52
53
54
H
'0000D0
H
'0000D4
H
'0000D8
ICRB6
Low