Datasheet

Rev. 3.00 Sep. 28, 2009 Page ix of xxxiv
REJ09B0384-0300
5.4 Interrupt Sources.................................................................................................................. 74
5.4.1 External Interrupts .................................................................................................. 74
5.4.2 Internal Interrupts ................................................................................................... 75
5.5 Interrupt Exception Handling Vector Table......................................................................... 76
5.6 Interrupt Control Modes and Interrupt Operation ................................................................ 78
5.6.1 Interrupt Control Mode 0........................................................................................ 80
5.6.2 Interrupt Control Mode 1........................................................................................ 82
5.6.3 Interrupt Exception Handling Sequence ................................................................. 85
5.6.4 Interrupt Response Times ....................................................................................... 87
5.6.5 DTC Activation by Interrupt................................................................................... 88
5.7 Usage Notes ......................................................................................................................... 90
5.7.1 Conflict between Interrupt Generation and Disabling ............................................ 90
5.7.2 Instructions that Disable Interrupts......................................................................... 91
5.7.3 Interrupts during Execution of EEPMOV Instruction............................................. 91
5.7.4 IRQ Status Registers (ISR16, ISR) ......................................................................... 91
Section 6 Bus Controller (BSC).........................................................................93
6.1 Features................................................................................................................................ 93
6.2 Bus Arbitration..................................................................................................................... 94
6.2.1 Overview................................................................................................................. 94
6.2.2 Priority of Bus Mastership ...................................................................................... 94
6.2.3 Bus Mastership Transfer Timing ............................................................................ 94
Section 7 Data Transfer Controller (DTC) ........................................................97
7.1 Features................................................................................................................................ 97
7.2 Register Descriptions ...........................................................................................................99
7.2.1 DTC Mode Register A (MRA) ............................................................................. 100
7.2.2 DTC Mode Register B (MRB).............................................................................. 101
7.2.3 DTC Source Address Register (SAR)................................................................... 101
7.2.4 DTC Destination Address Register (DAR)........................................................... 101
7.2.5 DTC Transfer Count Register A (CRA) ............................................................... 102
7.2.6 DTC Transfer Count Register B (CRB)................................................................ 102
7.2.7 DTC Enable Registers (DTCER).......................................................................... 103
7.2.8 DTC Vector Register (DTVECR)......................................................................... 104
7.2.9 Keyboard Comparator Control Register (KBCOMP)........................................... 105
7.2.10 Event Counter Control Register (ECCR).............................................................. 105
7.2.11 Event Counter Status Register (ECS) ................................................................... 106
7.3 DTC Event Counter ........................................................................................................... 107
7.3.1 Event Counter Handling Priority .......................................................................... 108
7.3.2 Usage Notes .......................................................................................................... 109