Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 68 of 710
REJ09B0384-0300
Table 5.2 Correspondence between Interrupt Source and ICR
Register
Bit Bit Name ICRA ICRB ICRC ICRD
7 ICRn7 IRQ0 A/D converter SCI_3 IRQ8 to IRQ11
6 ICRn6 IRQ1 FRT SCI_1 IRQ12 to IRQ15
5 ICRn5 IRQ2, IRQ3 ⎯ ⎯ ⎯
4 ICRn4 IRQ4, IRQ5 TMR_X IIC_0 ⎯
3 ICRn3 IRQ6, IRQ7 TMR_0 IIC_1 ⎯
2 ICRn2 DTC TMR_1 IIC_2, IIC_3 ⎯
1 ICRn1 WDT_0 TMR_Y LPC ⎯
0 ICRn0 WDT_1 ⎯ ⎯ ⎯
[Legend]]
n: A to D
⎯: Reserved. The write value should always be 0.
5.3.2 Address Break Control Register (ABRKCR)
ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an
address break is requested.
Bit Bit Name
Initial
Value R/W Description
7 CMF Undefined R Condition Match Flag
Address break source flag. Indicates that an address
specified by BARA to BARC is prefetched.
[Clearing condition]
When an exception handling is executed for an address
break interrupt.
[Setting condition]
When an address specified by BARA to BARC is
prefetched while the BIE flag is set to 1.
6 to 1 ⎯ All 0 R Reserved
These bits are always read as 0 and cannot be modified.
0 BIE 0 R/W Break Interrupt Enable
Enables or disables address break.
0: Disabled
1: Enabled