Datasheet
Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 66 of 710
REJ09B0384-0300
SYSCR
NMI input
IRQ input
Internal interrupt sources
SWDTEND to IBFI3
NMIEG
INTM1, INTM0
NMI input
IRQ input
ISR
ISCR
IER
ICR
Interrupt controller
Priority level
determination
Interrupt
request
Vector number
I, UI
CCR
CPU
ICR:
ISCR:
IER:
ISR:
SYSCR:
Interrupt control register
IRQ sense control register
IRQ enable register
IRQ status register
System control register
[Legend]
Figure 5.1 Block Diagram of Interrupt Controller
5.2 Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1 Pin Configuration
Symbol I/O Function
NMI Input Nonmaskable external interrupt
Rising edge or falling edge can be selected
IRQ15, IRQ14,
IRQ11 IRQ10,
IRQ7 to IRQ0
ExIRQ15 to
ExIRQ0
Input Maskable external interrupts
Rising edge, falling edge, or both edges, or level sensing can be
selected individually for each pin. Pin of IRQn or ExIRQn to input
IRQn (n = 15, 14, 11, 10, and 7 to 0) interrupt can be selected.