Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 65 of 710
REJ09B0384-0300
Section 5 Interrupt Controller
5.1 Features
• Two interrupt control modes
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
system control register (SYSCR).
• Priorities settable with ICR
An interrupt control register (ICR) is provided for setting interrupt priorities. Priority levels
can be set for each module for all interrupts except NMI.
• Three-level interrupt mask control
By means of the interrupt control mode, I and UI bits in CCR, and ICR, 3-level interrupt mask
control is performed.
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
• Twenty-nine external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level
sensing, can be selected for IRQn (n = 15, 14, 11, 10, and 7 to 0) and ExIRQm (m = 15 to 0).
• DTC control
The DTC can be activated by an interrupt request.