Datasheet

Rev. 3.00 Sep. 28, 2009 Page viii of xxxiv
REJ09B0384-0300
2.7.6 Immediate⎯#xx:8, #xx:16, or #xx:32.................................................................... 43
2.7.7 Program-Counter Relative⎯@(d:8, PC) or @(d:16, PC)....................................... 43
2.7.8 Memory Indirect⎯@@aa:8 ................................................................................... 44
2.7.9 Effective Address Calculation ................................................................................ 45
2.8 Processing States.................................................................................................................. 47
2.9 Usage Note........................................................................................................................... 49
2.9.1 Notes on Using the Bit Operation Instruction......................................................... 49
Section 3 MCU Operating Modes .....................................................................51
3.1 Operating Mode Selection ................................................................................................... 51
3.2 Register Descriptions ...........................................................................................................52
3.2.1 Mode Control Register (MDCR) ............................................................................ 52
3.2.2 System Control Register (SYSCR)......................................................................... 53
3.2.3 Serial Timer Control Register (STCR) ................................................................... 54
3.3 Operating Mode Descriptions.............................................................................................. 55
3.3.1 Mode 2.................................................................................................................... 55
3.4 Address Map........................................................................................................................ 55
Section 4 Exception Handling ...........................................................................57
4.1 Exception Handling Types and Priority............................................................................... 57
4.2 Exception Sources and Exception Vector Table.................................................................. 58
4.3 Reset .................................................................................................................................... 60
4.3.1 Reset Exception Handling ...................................................................................... 60
4.3.2 Interrupts after Reset............................................................................................... 61
4.3.3 On-Chip Peripheral Modules after Reset is Cancelled............................................ 61
4.4 Interrupt Exception Handling............................................................................................... 62
4.5 Trap Instruction Exception Handling................................................................................... 62
4.6 Stack Status after Exception Handling................................................................................. 63
4.7 Usage Note........................................................................................................................... 64
Section 5 Interrupt Controller............................................................................65
5.1 Features................................................................................................................................ 65
5.2 Input/Output Pins................................................................................................................. 66
5.3 Register Descriptions ...........................................................................................................67
5.3.1 Interrupt Control Registers A to D (ICRA to ICRD).............................................. 67
5.3.2 Address Break Control Register (ABRKCR) ......................................................... 68
5.3.3 Break Address Registers A to C (BARA to BARC)............................................... 69
5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................... 70
5.3.5 IRQ Enable Registers (IER16, IER) ....................................................................... 72
5.3.6 IRQ Status Registers (ISR16, ISR)......................................................................... 73