To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2153 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series H8S/2153 R4F2153 Rev.3.00 2009.
Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2.
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface The H8S/2153 Group are single-chip microcomputers made up of the high-speed H8S/2600 CPU employing Renesas Technology original architecture as its core, and the peripheral functions required to configure a system. The H8S/2600 CPU has an instruction set that is compatible with the H8/300 and H8/300H CPUs. Target Users: This manual was written for users who will be using the H8S/2153 Group in the design of application systems.
H8S/2153 Group manuals: Document Title Document No. H8S/2153 Group Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Software Manual REJ09B0139 User’s manuals for development tools: Document Title Document No.
Contents Section 1 1.1 1.2 1.3 Section 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Overview..............................................................................................1 Overview................................................................................................................................ 1 Internal Block Diagram.......................................................................................................... 3 Pin Description..............................................
2.8 2.9 2.7.6 Immediate⎯#xx:8, #xx:16, or #xx:32.................................................................... 43 2.7.7 Program-Counter Relative⎯@(d:8, PC) or @(d:16, PC)....................................... 43 2.7.8 Memory Indirect⎯@@aa:8 ................................................................................... 44 2.7.9 Effective Address Calculation ................................................................................ 45 Processing States.......................................
5.4 5.5 5.6 5.7 Interrupt Sources.................................................................................................................. 74 5.4.1 External Interrupts .................................................................................................. 74 5.4.2 Internal Interrupts ................................................................................................... 75 Interrupt Exception Handling Vector Table............................................................
7.4 7.5 7.6 7.7 7.8 7.9 Activation Sources............................................................................................................. 109 Location of Register Information and DTC Vector Table ................................................. 110 Operation ........................................................................................................................... 112 7.6.1 Normal Transfer Mode ...............................................................................
8.3.7 Pin Functions ........................................................................................................ 136 8.3.8 Port 3 Input Pull-Up MOS .................................................................................... 136 8.4 Port 4.................................................................................................................................. 137 8.4.1 Port 4 Data Direction Register (P4DDR).............................................................. 137 8.4.
8.11.2 Port E Output Data Register (PEODR)................................................................. 171 8.11.3 Port E Input Data Register (PEPIN) ..................................................................... 171 8.11.4 Pin Functions ........................................................................................................ 172 8.12 Change of Peripheral Function Pins................................................................................... 175 8.12.
10.5.4 Switching of Internal Clock and FRC Operation .................................................. 208 Section 11 8-Bit Timer (TMR) ..........................................................................211 11.1 Features.............................................................................................................................. 211 11.2 Register Descriptions ......................................................................................................... 214 11.2.
12.6.2 12.6.3 12.6.4 12.6.5 12.6.6 Conflict between Timer Counter (TCNT) Write and Increment........................... 248 Changing Values of CKS2 to CKS0 Bits.............................................................. 248 Changing Value of PSS Bit .................................................................................. 248 Switching between Watchdog Timer Mode and Interval Timer Mode................. 249 System Reset by RESO Signal ............................................................
13.7.3 Block Transfer Mode ............................................................................................ 300 13.7.4 Receive Data Sampling Timing and Reception Margin........................................ 301 13.7.5 Initialization .......................................................................................................... 302 13.7.6 Serial Data Transmission (Except in Block Transfer Mode) ................................ 303 13.7.
2 15.3.8 I C Bus Extended Control Register (ICXR).......................................................... 353 2 15.3.9 I C SMBus Control Register (ICSMBCR)............................................................ 357 15.4 Operation ........................................................................................................................... 359 2 15.4.1 I C Bus Data Format ............................................................................................. 359 15.4.
16.3.21 BT Status Register 0 (BTSR0).............................................................................. 451 16.3.22 BT Status Register 1 (BTSR1).............................................................................. 454 16.3.23 BT Control Status Register 0 (BTCSR0) .............................................................. 457 16.3.24 BT Control Status Register 1 (BTCSR1) .............................................................. 458 16.3.25 BT Control Register (BTCR)..............
17.7.3 17.7.4 17.7.5 17.7.6 17.7.7 Influences on Absolute Accuracy ......................................................................... 503 Setting Range of Analog Power Supply and Other Pins....................................... 503 Notes on Board Design ......................................................................................... 503 Notes on Noise Countermeasures ......................................................................... 504 Note on the Usage in Software Standby Mode ...
20.3.4 ID Code Register (SDIDR) ................................................................................... 616 20.4 Operation ........................................................................................................................... 617 20.4.1 TAP Controller State Transitions.......................................................................... 617 20.4.2 JTAG Reset...........................................................................................................
.8.3 DTC Module Stop Mode ...................................................................................... 647 22.8.4 Notes on Subclock Usage ..................................................................................... 647 Section 23 List of Registers...............................................................................649 23.1 Register Addresses (Address Order).................................................................................. 649 23.2 Register Bits................
Figures Section 1 Overview Figure 1.1 Figure 1.2 Internal Block Diagram ............................................................................................ 3 Pin Assignment (BP-112) ......................................................................................... 4 Section 2 CPU Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Figure 2.9 Figure 2.9 Figure 2.10 Figure 2.11 Figure 2.12 Figure 2.13 Exception Vector Table (Normal Mode) .............
Figure 5.6 Figure 5.7 Figure 5.8 Figure 5.9 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1................................................................................... 84 Interrupt Exception Handling ................................................................................. 86 Interrupt Control for DTC....................................................................................... 88 Conflict between Interrupt Generation and Disabling .....................
Section 10 16-Bit Free-Running Timer (FRT) Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Figure 10.7 Figure 10.8 Figure 10.9 Figure 10.10 Block Diagram of 16-Bit Free-Running Timer..................................................... 194 Increment Timing with Internal Clock Source...................................................... 201 Timing of Output Compare A Output...................................................................
Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Figure 13.9 Figure 13.9 Figure 13.10 Figure 13.11 Figure 13.12 Figure 13.13 Figure 13.13 Figure 13.14 Figure 13.15 Figure 13.16 Figure 13.17 Figure 13.18 Figure 13.19 Figure 13.20 Figure 13.21 Figure 13.22 Figure 13.23 Figure 13.24 Figure 13.25 Figure 13.26 Figure 13.27 Figure 13.28 Figure 13.29 Figure 13.30 Figure 13.31 Figure 13.32 Figure 13.33 Figure 13.34 Receive Data Sampling Timing in Asynchronous Mode............................
Figure 13.35 Figure 13.36 Figure 13.37 Figure 13.38 Figure 13.39 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............ 314 Pin States during Transmission in Clock Synchronous Mode (Internal Clock)... 315 Sample Flowchart for Mode Transition during Reception.................................... 316 Switching from SCK Pins to Port Pins ................................................................. 317 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins .......
Figure 15.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1) ....... 376 Figure 15.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) .............. 377 Figure 15.21 Slave Receive Mode Operation Timing Example (1) (MLS = ACKB = 0, HNDS = 0)........................................................................... 379 Figure 15.22 Slave Receive Mode Operation Timing Example (2) (MLS = ACKB = 0, HNDS = 0).....................................................................
Figure 17.4 Figure 17.5 Figure 17.6 Figure 17.7 Figure 17.8 Figure 17.9 Figure 17.10 A/D Conversion Timing ....................................................................................... 497 Timing of External Trigger Input ......................................................................... 499 A/D Conversion Accuracy Definitions ................................................................. 501 A/D Conversion Accuracy Definitions ...........................................................
Section 21 Clock Pulse Generator Figure 21.1 Figure 21.2 Figure 21.3 Figure 21.4 Figure 21.5 Block Diagram of Clock Pulse Generator............................................................. 625 Typical Connection to Crystal Resonator ............................................................. 626 Equivalent Circuit of Crystal Resonator ............................................................... 626 Example of External Clock Input ....................................................................
Tables Section 1 Overview................................................................................................ Table 1.1 Table 1.2 Pin Assignment in Each Operating Mode................................................................. 5 Pin Functions ............................................................................................................ 9 Section 2 CPU........................................................................................................ Table 2.
Table 5.6 Table 5.7 Table 5.8 Table 5.9 Operations and Control Signal Functions in Each Interrupt Control Mode............ 80 Interrupt Response Times ....................................................................................... 87 Number of States in Interrupt Handling Routine Execution Status ........................ 87 Interrupt Source Selection and Clearing Control.................................................... 89 Section 7 Data Transfer Controller (DTC) Table 7.1 Table 7.2 Table 7.
Table 11.2 Table 11.3 Table 11.4 Registers Accessible by TMR_X/TMR_Y ........................................................... 223 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X ....... 228 Switching of Internal Clocks and TCNT Operation.............................................. 232 Section 12 Watchdog Timer (WDT) Table 12.1 Table 12.2 Pin Configuration.................................................................................................. 237 WDT Interrupt Source ......
Section 16 LPC Interface (LPC) Table 16.1 Table 16.2 Table 16.3 Table 16.4 Table 16.5 Table 16.6 Table 16.7 Table 16.8 Table 16.9 Table 16.10 Pin Configuration.................................................................................................. 407 LADR1, LADR2 Initial Values ............................................................................ 420 Host Register Selection.........................................................................................
Section 20 Boundary Scan (JTAG) Table 20.1 Table 20.2 Table 20.3 Pin Configuration.................................................................................................. 607 JTAG Register Serial Transfer.............................................................................. 608 Correspondence between Pins and Boundary Scan Register ................................ 611 Section 21 Clock Pulse Generator Table 21.1 Table 21.2 Table 21.3 Damping Resistance Values ............................
Rev. 3.00 Sep.
Section 1 Overview Section 1 Overview 1.
Section 1 Overview • General I/O ports I/O pins: 65 Input-only pins: 9 • Supports various power-down states • Compact package Package (code) Body Size Pin Pitch PLBG0112GA-A (BP-112) 10 × 10 mm 0.8 mm Rev. 3.00 Sep.
Section 1 Overview Internal Block Diagram Port E Port C PC7/PWX3 PC6/PWX2 PC3/SDA3 PC2/SCL3 PC1/SDA2 PC0/SCL2 Port A Bus controller EVC LPC SCI WDT × 2 channels 16-bit FRT 14-bit PWM × 4 channels IIC × 4 channels 10-bit A/D JTAG 8-bit timer × 4 channels Peripheral address bus Peripheral data bus RAM PE7/SERIRQ PE6/LCLK PE5/LRESET PE4/LFRAME PE3/LAD3 PE2/LAD2 PE1/LAD1 PE0/LAD0 PA7/EVENT7 PA6/EVENT6 PA5/EVENT5 PA4/EVENT4 PA3/EVENT3 PA2/EVENT2 PA1/EVENT1 PA0/EVENT0 Internal address bus In
Section 1 Overview 1.3 Pin Description 1.3.
Section 1 Overview 1.3.2 Table 1.1 Pin Assignment in Each Operating Mode Pin Assignment in Each Operating Mode Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview 1.3.3 Pin Functions Table 1.2 Pin Functions Pin No. Type Symbol BP-112 Power supply VCC A1, J1, G9 Input Power supply pins. Connect all these pins to the system power supply. Connect the bypass capacitor between VCC and VSS (near VCC). VCL E1 Input External capacitance pin for internal step-down power. Connect this pin to Vss through an external capacitor (that is located near this pin) to stabilize internal step-down power. VSS D3, H4, E11, D8, B4 Input Ground pins.
Section 1 Overview Pin No. Type Symbol BP-112 I/O Name and Function Interrupts NMI E4 Input Nonmaskable interrupt request input pin IRQ15, IRQ14, IRQ11, IRQ10, IRQ7 to IRQ0 C1, C2, C5, Input B5, D4, B1, B2, D5, A5, D6; B6, A6 These pins request a maskable interrupt. Selectable to which pin of IRQn or ExIRQn to insert IRQ15 to IRQ0 interrupts.
Section 1 Overview Pin No. Type Symbol BP-112 I/O Name and Function A/D converter AN7 to AN0 H8, K11, K10, L11, L10, K9, L9, K8 Input Analog input pins AVCC J10 Input Analog power supply pins for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, these pins should be connected to the system power supply (+3.3 V). AVref J11 Input Reference voltage input pin for the A/D converter and D/A converter.
Section 1 Overview Pin No.
Section 2 CPU Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.
Section 2 CPU ⎯ 16 ÷ 8-bit register-register divide: 12 states ⎯ 16 × 16-bit register-register multiply: 3 states ⎯ 32 ÷ 16-bit register-register divide: 20 states • Two CPU operating modes ⎯ Normal mode* ⎯ Advanced mode • Power-down state ⎯ Transition to power-down state by the SLEEP instruction ⎯ CPU clock speed selection Note: * Normal mode is not available in this LSI. 2.1.
Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements: • More general registers and control registers ⎯ Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. • Expanded address space ⎯ Normal mode supports the same 64-kbyte address space as the H8/300 CPU. ⎯ Advanced mode supports a maximum 16-Mbyte address space.
Section 2 CPU 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. • Address Space Linear access to a 64-kbyte maximum address space is provided.
Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Exception vector 1 Exception vector 2 Exception vector 3 Exception vector table Exception vector 4 Exception vector 5 Exception vector 6 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) EXR*1 SP (SP * 2 Reserved*1,*3 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3.
Section 2 CPU 2.2.2 Advanced Mode • Address Space Linear access to a 16-Mbyte maximum address space is provided. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. • Instruction Set All instructions and addressing modes can be used.
Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
Section 2 CPU 2.4 Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate register (MAC).
Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). 2.4.3 Extended Control Register (EXR) EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Section 2 CPU Bit Bit Name Initial Value 1 V Undefined R/W R/W Description Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.
Section 2 CPU 2.5 Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers.
Section 2 CPU Data Type Register Number Word data Rn Data Format 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 3.00 Sep.
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.6 Instruction Set The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1. Table 2.
Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
Section 2 CPU Symbol Description :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI.
Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) 1 Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B BLD B BILD B C ⊕ [∼( of )] → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. (
Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc ⎯ Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA ⎯ Starts trap-instruction exception handling. RTE ⎯ Returns from an exception-handling routine. SLEEP ⎯ Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves general register or memory contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B ⎯ if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W ⎯ if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. Rev. 3.00 Sep.
Section 2 CPU 2.6.2 Basic Instruction Formats The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.11 shows examples of instruction formats. • Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand.
Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect.
Section 2 CPU 2.7.3 Register Indirect with Displacement⎯@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.
Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address Normal Mode* Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) Program instruction address H'000000 to H'FFFFFF 24 bits (@aa:24) Note: Normal mode is not available in this LSI. 2.7.
Section 2 CPU 2.7.8 Memory Indirect⎯@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long.
Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents.
Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data.
Section 2 CPU 2.8 Processing States The H8S/2600 CPU has four main processing states: the reset state, exception handling state, program execution state and power-down state. Figure 2.13 indicates the state transitions. • Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
Section 2 CPU End of bus request Bus request Program execution state End of bus request SLEEP instruction with PSS = 0 and SSBY = 1 Bus request SLEEP instruction with SSBY = 0 Bus-released state Request for exception handling End of exception handling Sleep mode Interrupt request Exception-handling state External interrupt request Software standby mode RES = high Reset state*1 STBY = High, RES = Low Hardware standby mode*2 Power-down state Notes: 1.
Section 2 CPU 2.9 Usage Note 2.9.1 Notes on Using the Bit Operation Instruction Instructions BSET, BCLR, BNOT, BST, and BIST read data in byte units, and write data in byte units after bit operation. Therefore, attention must be paid when these instructions are used for ports or registers including write-only bits. Instruction BCLR can be used to clear the flag in the internal I/O register to 0.
Section 2 CPU Rev. 3.00 Sep.
Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection This MCU supports three operating modes (modes 2, 4, and 6). The operating mode is determined by the setting of the mode pins (MD2 and MD1). Table 3.1 shows the MCU operating mode selection. Table 3.
Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) • Serial timer control register (STCR) 3.2.1 Mode Control Register (MDCR) MDCR is used to set an operating mode and to monitor the current operating mode. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved The initial value should not be changed.
Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables register access to the on-chip peripheral modules, and enables or disables on-chip RAM address space. Bit Bit Name Initial Value R/W Description 7 6 ⎯ All 0 R/W Reserved 5 INTM1 0 R 4 INTM0 0 R/W The initial value should not be changed.
Section 3 MCU Operating Modes 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Bit Bit Name Initial Value R/W Description 7 IICX2 0 R/W IIC Transfer Rate Select 2, 1 and 0 6 IICX1 0 R/W 5 IICX0 0 R/W These bits control the IIC operation. These bits select a transfer rate in master mode together with 2 bits CKS2 to CKS0 in the I C bus mode register (ICMR).
Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 2 The CPU can access a 16 Mbytes address space in advanced mode. The on-chip ROM is enabled. 3.4 Address Map Figure 3.1 shows an address map in operating mode. Rev. 3.00 Sep.
Section 3 MCU Operating Modes ROM: 512 kbytes, RAM: 40 kbytes Mode 2 Advanced mode Single-chip mode H'000000 On-chip ROM H'07FFFF H'FF0000 H'FF07FF H'FF0800 Reserved area On-chip RAM (36 kbytes) H'FF97FF H'FF9800 Reserved area H'FFBFFF H'FFE080 H'FFEFFF On-chip RAM (3,968 bytes) H'FFF800 H'FFFE3F H'FFFE40 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Figure 3.1 Address Map Rev. 3.00 Sep.
Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.
Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.
Section 4 Exception Handling Vector Address Exception Source Vector Number Advanced Mode Internal interrupt* 24 ⎜ 29 H'000060 to H'000063 ⎜ H'000074 to H'000077 Reserved for system use 30 ⎜ 33 H'000078 to H'00007B ⎜ H'000084 to H'000087 Internal interrupt* 34 ⎜ 55 H'000088 to H'00008B ⎜ H'0000DC to H'0000DF External interrupt IRQ8 56 H'0000E0 to H'0000E3 IRQ9 57 H'0000E4 to H'0000E7 IRQ10 58 H'0000E8 to H'0000EB IRQ11 59 H'0000EC to H'0000EF IRQ12 60 H'0000F0 to H'0000F3 Internal
Section 4 Exception Handling 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer.
Section 4 Exception Handling Vector fetch Internal processing Prefetch of first program instruction φ RES Internal address bus (1) U (1) L (3) Internal read signal High Internal write signal Internal data bus (2) U (2) L (4) (1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002 (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)U + (2)L) (4) First program instruction Figure 4.1 Reset Sequence 4.3.
Section 4 Exception Handling 4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI and IRQ15 to IRQ0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, see section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1.
Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Advanced mode SP CCR PC (24 bits) Figure 4.2 Stack Status after Exception Handling Rev. 3.00 Sep.
Section 4 Exception Handling 4.7 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.
Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Priority levels can be set for each module for all interrupts except NMI.
Section 5 Interrupt Controller CPU INTM1, INTM0 SYSCR NMIEG NMI input NMI input IRQ input IRQ input ISR ISCR IER Interrupt request Vector number Priority level determination I, UI CCR Internal interrupt sources SWDTEND to IBFI3 ICR Interrupt controller [Legend] ICR: ISCR: IER: ISR: SYSCR: Interrupt control register IRQ sense control register IRQ enable register IRQ status register System control register Figure 5.1 Block Diagram of Interrupt Controller 5.2 Input/Output Pins Table 5.
Section 5 Interrupt Controller 5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR), and for details on the IRQ sense port select registers (ISSR16 and ISSR), see section 8.12.1, IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR).
Section 5 Interrupt Controller Table 5.2 Correspondence between Interrupt Source and ICR Register Bit Bit Name ICRA ICRB ICRC ICRD 7 ICRn7 IRQ0 A/D converter SCI_3 IRQ8 to IRQ11 6 ICRn6 IRQ1 FRT SCI_1 IRQ12 to IRQ15 5 ICRn5 IRQ2, IRQ3 ⎯ ⎯ ⎯ 4 ICRn4 IRQ4, IRQ5 TMR_X IIC_0 ⎯ 3 ICRn3 IRQ6, IRQ7 TMR_0 IIC_1 ⎯ 2 ICRn2 DTC TMR_1 IIC_2, IIC_3 ⎯ 1 ICRn1 WDT_0 TMR_Y LPC ⎯ 0 ICRn0 WDT_1 ⎯ ⎯ ⎯ [Legend]] n: A to D ⎯: Reserved. The write value should always be 0.
Section 5 Interrupt Controller 5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. • BARA Bit Bit Name Initial Value R/W Description 7 to 0 A23 to A16 All 0 R/W Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus.
Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ15, IRQ14, IRQ11, IRQ10, and IRQ7 to IRQ0 or pins ExIRQ15 to ExIRQ0.
Section 5 Interrupt Controller • ISCRH Bit Bit Name Initial Value R/W Description 7 IRQ7SCB 0 R/W 6 IRQ7SCA 0 R/W IRQn Sense Control B IRQn Sense Control A 5 IRQ6SCB 0 R/W 4 IRQ6SCA 0 R/W 3 IRQ5SCB 0 R/W 2 IRQ5SCA 0 R/W 1 IRQ4SCB 0 R/W 0 IRQ4SCA 0 R/W 00: Interrupt request generated at low level of IRQn or ExIRQn input 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Inter
Section 5 Interrupt Controller 5.3.5 IRQ Enable Registers (IER16, IER) The IER registers control the enabling and disabling of interrupt requests IRQ15 to IRQ0. • IER16 Bit Bit Name 7 to 0 IRQ15E to IRQ8E Note: * Initial Value R/W Description All 0 R/W IRQn Enable (n = 15 to 8) The IRQn interrupt request is enabled when this bit is 1. IRQn stands for IRQ15, IRQ14, IRQ11, and IRQ10.
Section 5 Interrupt Controller 5.3.6 IRQ Status Registers (ISR16, ISR) The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests.
Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts The external interrupts are NMI are IRQ15 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits.
Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit S IRQn interrupt request Q R IRQn* input or ExIRQn input Clear signal n = 15 to 0 Note: * IRQn stands for IRQ15, IRQ14, IRQ11, IRQ10, and IRQ7 to IRQ0. Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 5.4.
Section 5 Interrupt Controller 5.5 Interrupt Exception Handling Vector Table Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. An interrupt control level can be specified for a module to which an ICR bit is assigned.
Section 5 Interrupt Controller Origin of Interrupt Source Name Vector Address Vector Number Advanced Mode IRQ8 IRQ9 IRQ10 IRQ11 56 57 58 59 IRQ12 IRQ13 IRQ14 IRQ15 TMR_0 ICR Priority H'0000E0 H'0000E4 H'0000E8 H'0000EC ICRD7 High 60 61 62 63 H'0000F0 H'0000F4 H'0000F8 H'0000FC ICRD6 CMIA0 (Compare match A) CMIB0 (Compare match B) OVI0 (Overflow) 64 65 66 H'000100 H'000104 H'000108 ICRB3 TMR_1 CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) 68 69 70 H'000110 H'000114 H'00
Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes. Table 5.
Section 5 Interrupt Controller Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.5 shows the interrupts selected in each interrupt control mode. Table 5.
Section 5 Interrupt Controller Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Setting Interrupt Acceptance Control 3-Level Control Default Priority I UI ICR Determination T (Trace) Control Mode INTM1 INTM0 0 0 0 O IM ⎯ PR O ⎯ 1 O IM IM PR O ⎯ 1 [Legend] O: Interrupt operation control performed IM: Used as an interrupt mask bit PR: Sets priority ⎯: Not used 5.6.
Section 5 Interrupt Controller Program execution state Interrupt generated? No Yes Yes NMI No No An interrupt with interrupt control level 1? Hold pending Yes No No IRQ0 IRQ0 Yes No Yes IRQ1 Yes No IRQ1 Yes IBFI3 IBFI3 Yes Yes I=0 No Yes Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 3.00 Sep.
Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting. • An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0. When the I bit is set to 1, the interrupt request is held pending. The EVENTI interrupt is enabled or disabled by the I bit.
Section 5 Interrupt Controller Figure 5.6 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority).
Section 5 Interrupt Controller Program execution state No Interrupt generated? Yes Yes NMI No No An interrupt with interrupt control level 1? Hold pending Yes IRQ0 Yes No No IRQ0 No Yes IRQ1 No IRQ1 Yes Yes IBFI3 IBFI3 Yes Yes I=0 No I=0 Yes No UI = 0 No Yes Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 Rev. 3.00 Sep.
Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 3.00 Sep.
REJ09B0384-0300 Rev. 3.00 Sep. 28, 2009 Page 86 of 710 Figure 5.7 Interrupt Exception Handling (2) (4) (3) (5) (7) (1) Internal data bus (1) (2) (4) Instruction prefetch (3) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) Instruction code (not executed) Instruction prefetch address (Instruction is not executed.
Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.7 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.7 are explained in table 5.8. Table 5.7 No.
Section 5 Interrupt Controller 5.6.5 DTC Activation by Interrupt The DTC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Both of the above For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller (DTC). Figure 5.8 shows a block diagram of the DTC and interrupt controller.
Section 5 Interrupt Controller Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.9 summarizes interrupt source selection and interrupt source clearing control according to the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB in the DTC. Table 5.
Section 5 Interrupt Controller 5.7 Usage Notes 5.7.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction.
Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.
Section 5 Interrupt Controller Rev. 3.00 Sep.
Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC). The BSC has a bus arbitration function, and controls the operation of the internal bus masters – CPU and data transfer controller (DTC). 6.1 Features • Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC.
Section 6 Bus Controller (BSC) 6.2 Bus Arbitration 6.2.1 Overview The BSC has a bus arbiter that arbitrates bus master operations. There are two bus masters – the CPU and DTC – that perform read/write operations while they have bus mastership. 6.2.2 Priority of Bus Mastership Each bus master requests the bus mastership by means of a bus mastership request signal.
Section 6 Bus Controller (BSC) (2) DTC The DTC sends the bus arbiter a request for the bus mastership when a request for DTC activation occurs. The DTC releases the bus mastership after a series of processes has completed. Rev. 3.00 Sep.
Section 6 Bus Controller (BSC) Rev. 3.00 Sep.
Section 7 Data Transfer Controller (DTC) Section 7 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1.
Section 7 Data Transfer Controller (DTC) Internal address bus CPU interrupt request [Legend] MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERE: DTVECR: Internal data bus DTC mode register A, B DTC transfer count register A, B DTC source address register DTC destination address register DTC enable registers A to E DTC vector register Figure 7.1 Block Diagram of DTC Rev. 3.00 Sep.
Section 7 Data Transfer Controller (DTC) 7.2 Register Descriptions The DTC has the following registers. • DTC mode register A (MRA) • DTC mode register B (MRB) • DTC source address register (SAR) • DTC destination address register (DAR) • DTC transfer count register A (CRA) • DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU.
Section 7 Data Transfer Controller (DTC) 7.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Bit Name Initial Value R/W 7 SM1 Undefined ⎯ 6 SM0 Description Source Address Mode 1 and 0 These bits specify an SAR operation after a data transfer.
Section 7 Data Transfer Controller (DTC) 7.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Bit Name Initial Value R/W 7 CHNE Undefined ⎯ Description DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, see section 7.6.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of data transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed.
Section 7 Data Transfer Controller (DTC) 7.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal transfer mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
Section 7 Data Transfer Controller (DTC) 7.2.7 DTC Enable Registers (DTCER) DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers: DTCERA to DTCERE. The correspondence between interrupt sources and DTCE bits is shown in tables 7.1 and 7.4. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR.
Section 7 Data Transfer Controller (DTC) 7.2.8 DTC Vector Register (DTVECR) DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit Bit Name Initial Value R/W Description 7 SWDTE 0 R/W DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit.
Section 7 Data Transfer Controller (DTC) 7.2.9 Keyboard Comparator Control Register (KBCOMP) KBCOMP enables or disables the comparator scan function of event counter. Bit Bit Name Initial Value R/W 7 EVENTE 0 R/W Description Event Count Enable 0: Disables event count function 1: Enables event count function 6, 5 ⎯ All 0 R Reserved These bits are always read as 0 and cannot be modified. 4 to 0 ⎯ All 0 R/W Reserved The initial value should not be changed. 7.2.
Section 7 Data Transfer Controller (DTC) Bit Bit Name 2 to 0 ECSB2 to ECSB0 Initial Value R/W Description All 0 R/W Event Counter Channel Select 2 to 0 These bits select pins for event counter input. A series of pins are selected starting from EVENT0. When PAnDDR is set to 1, inputting events to EVENT0 to EVENT7 is ignored.
Section 7 Data Transfer Controller (DTC) 7.3 DTC Event Counter To count events of EVENT 0 to EVENT7 by the DTC event counter function, set DTC as below. Table 7.2 DTC Event Counter Conditions Register Bit Bit Name MRA 7, 6 SM1, SM0 00: SAR is fixed. 5, 4 DM1, DM0 00: DAR is fixed.
Section 7 Data Transfer Controller (DTC) The EVENTI interrupt request activates the DTC and transfers data from RAM to RAM in the same address. Data is incremented in the DTC. The lower five bits of SAR and DAR are replaced with address code that is generated by the ECS flag status. When the DTC transfer is completed, the ECS flag for transfer is cleared. Table 7.3 Flag Status/Address Code ECS 7 1 7.3.
Section 7 Data Transfer Controller (DTC) 7.3.2 Usage Notes There are following usage notes for this event counter because it uses the DTC. 1. Continuous events that are input from the same pin and out of DTC handling are ignored because the count up is operated by means of the DTC. 2. If some events are generated in short intervals, the priority of event counter handling is not ordered and events are not handled in order of arrival.
Section 7 Data Transfer Controller (DTC) 7.5 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFEC00 to H'FFEFFF). Register information should be located at an address that is a multiple of four within the range. The method for locating the register information in address space is shown in figure 7.3. Locate MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register information.
Section 7 Data Transfer Controller (DTC) DTC vector address Register information start address Register information Chain transfer Figure 7.4 Correspondence between DTC Vector Address and Register Information Table 7.
Section 7 Data Transfer Controller (DTC) 7.6 Operation The DTC stores register information in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to on-chip RAM. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels.
Section 7 Data Transfer Controller (DTC) 7.6.1 Normal Transfer Mode In normal transfer mode, one activation source transfers one byte or one word of data. Table 7.5 lists the register functions in normal transfer mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has been completed, a CPU interrupt can be requested. Table 7.
Section 7 Data Transfer Controller (DTC) 7.6.2 Repeat Transfer Mode In repeat transfer mode, one activation source transfers one byte or one word of data. Table 7.6 lists the register functions in repeat transfer mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has been completed, the initial states of the transfer counter and the address register that is specified as the repeat area is restored, and transfer is repeated.
Section 7 Data Transfer Controller (DTC) 7.6.3 Block Transfer Mode In block transfer mode, one activation source transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 7.7 lists the register functions in block transfer mode. The block size can be between 1 and 256. When the transfer of one block ends, the initial state of the block size counter and the address register that is specified as the block area is restored.
Section 7 Data Transfer Controller (DTC) 7.6.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.9 shows the overview of chain transfer operation.
Section 7 Data Transfer Controller (DTC) 7.6.5 Interrupt Sources An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control by the interrupt controller.
Section 7 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information read Transfer information write Figure 7.
Section 7 Data Transfer Controller (DTC) Table 7.8 DTC Execution Status Mode Vector Read I Register Information Read/Write J Data Read K Data Write L Internal Operations M Normal transfer 1 6 1 1 3 Repeat transfer 1 6 1 1 3 Block transfer 1 6 N N 3 [Legend] N: Block size (initial setting of CRAH and CRAL) Table 7.
Section 7 Data Transfer Controller (DTC) required for the DTC operation is 13 states. The time from activation to the end of data write is 10 states. 7.7 Procedures for Using DTC 7.7.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4.
Section 7 Data Transfer Controller (DTC) 7.8 Examples of Use of the DTC 7.8.1 Normal Transfer Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal transfer mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
Section 7 Data Transfer Controller (DTC) 7.8.2 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the transfer destination address is H'2000. The vector number is H′60, so the vector address is H'04C0. 1.
Section 7 Data Transfer Controller (DTC) 7.9 Usage Notes 7.9.1 Module Stop Mode Setting DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the initial state, DTC operation is enabled. Access to DTC registers is disabled when module stop mode is set. Note that when the DTC is being activated, module stop mode cannot be specified. For details, refer to section 22, Power-Down Modes. 7.9.2 On-Chip RAM MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM.
Section 7 Data Transfer Controller (DTC) Rev. 3.00 Sep.
Section 8 I/O Ports Section 8 I/O Ports Table 8.1 is a summary of the port functions. The pins of each port also function as input/output pins of peripheral modules and interrupt input pins. Each input/output port includes a data direction register (DDR) that controls input/output and a data register (DR) that stores output data. DDR and DR are not provided for an input-only port. Ports 1 to 4, 6, and A have built-in input pull-up MOSs.
Section 8 I/O Ports Port Description Single-Chip Mode I/O Status Port 3 General I/O port also functioning as debounce input P37/ExDB7 Built-in input pull-up MOS P36/ExDB6 P35/ExDB5 P34/ExDB4 P33/ExDB3 P32/ExDB2 P31/ExDB1 P30/ExDB0 Port 4 General I/O port also functioning as interrupt input, retain state output, and debounce input P47/IRQ7/RS7/DB7/HC7 P46/IRQ6/RS6/DB6/HC6 P45/IRQ5/RS5/DB5/HC5 P44/IRQ4/RS4/DB4/HC4 Built-in input pull-up MOS (sink current 12 mA) P43/IRQ3/RS3/HC3 P42/IRQ2/RS2/HC2
Section 8 I/O Ports Port Description Single-Chip Mode I/O Status Port 8 General I/O port also functioning as A/D converter external trigger input, interrupt input, SCI_1 and SCI_3 input/output, and IIC_0 and IIC_1 input/output P87/ExIRQ15/TxD3/ADTRG NMOS pushpull output P86/ExIRQ14/RxD3 P85/ExIRQ13/SCK1 P84/ExIRQ12/SCK3 P83/ExIRQ11/SDA1 P82/ExIRQ10/SCL1 P81/ExIRQ9/SDA0 P80/ExIRQ8/SCL0 Port A General I/O port also functioning as DTC event counter input PA7/EVENT7 PA6/EVENT6 Built-in input pull-u
Section 8 I/O Ports 8.1 Port 1 Port 1 is an 8-bit I/O port. Port 1 has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 pull-up MOS control register (P1PCR) 8.1.1 Port 1 Data Direction Register (P1DDR) The individual bits of P1DDR specify input or output for the pins of port 1.
Section 8 I/O Ports 8.1.3 Port 1 Pull-Up MOS Control Register (P1PCR) P1PCR controls the port 1 built-in input pull-up MOSs. Bit Bit Name Initial Value R/W Description 7 P17PCR 0 R/W 6 P16PCR 0 R/W When the pins are in input state, the corresponding input pull-up MOS is turned on when a P1PCR bit is set to 1. 5 P15PCR 0 R/W 4 P14PCR 0 R/W 3 P13PCR 0 R/W 2 P12PCR 0 R/W 1 P11PCR 0 R/W 0 P10PCR 0 R/W 8.1.
Section 8 I/O Ports 8.2 Port 2 Port 2 is a 4-bit I/O port. Port 2 has the following registers. • Port 2 data direction register (P2DDR) • Port 2 data register (P2DR) • Port 2 pull-up MOS control register (P2PCR) 8.2.1 Port 2 Data Direction Register (P2DDR) The individual bits of P2DDR specify input or output for the pins of port 2.
Section 8 I/O Ports 8.2.3 Port 2 Pull-Up MOS Control Register (P2PCR) P2PCR controls the port 2 built-in input pull-up MOSs. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved 6 ⎯ 0 R/W 5 ⎯ 0 R/W 4 ⎯ 0 R/W 3 P23PCR 0 R/W 2 P22PCR 0 R/W 1 P21PCR 0 R/W 0 P20PCR 0 R/W 8.2.4 When the pins are in input state, the corresponding input pull-up MOS is turned on when a P2PCR bit is set to 1.
Section 8 I/O Ports 8.3 Port 3 Port 3 is an 8-bit I/O port. Port 3 pins also function as de-bounce input. Port 3 has the following registers. • Port 3 data direction register (P3DDR) • Port 3 data register (P3DR) • Port 3 pull-up MOS control register (P3PCR) • Noise canceler enable register (P3NCE) • Noise canceler mode control register (P3NCMC) • Noise cancel cycle setting register (NCCS) 8.3.
Section 8 I/O Ports 8.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Bit Name Initial Value R/W Description 7 P37DR 0 6 P36DR 0 5 P35DR 0 4 P34DR 0 R/W P3DR stores output data for the port 3 pins that are used as the general output port. R/W If a port 3 read is performed while the P3DDR bits are R/W set to 1, the P3DR values are read. When the P3DDR R/W bits are cleared to 0, 1 is read.
Section 8 I/O Ports 8.3.4 Noise Canceler Enable Register (P3NCE) P3NCE enables or disables the noise canceler circuit at port 3. Bit Bit Name Initial Value R/W Description 7 P37NCE 0 6 P36NCE 0 5 P35NCE 0 4 P34NCE 0 R/W When the noise canceler circuit is enabled, the pin state is fetched in the P3DR in the sampling cycle set by the R/W NCCS. R/W The operating state changes according to the other R/W control bits. Check the pin functions.
Section 8 I/O Ports 8.3.6 Noise Canceler Cycle Setting Register (NCCS) NCCS controls the sampling cycles of the noise canceler. Bit Bit Name Initial Value R/W Description 7 to 3 ⎯ Undefined R/W Reserved 2 NCCK2 0 1 NCCK1 0 R/W These bits set the sampling cycle of the noise R/W cancelers. 0 NCCK0 0 The read value is undefined. R/W • When φ = 25 MHz 000: 80 ns φ/2 001: 1.28 μs φ/32 010: 20.48 μs φ/512 011: 327.7 μs φ/8192 100: 1.31 ms φ/32768 101: 2.62 ms φ/65536 110: 5.
Section 8 I/O Ports P3n input 1 expected P3nDR 0 expected P3nDR (n = 7 to 0) Figure 8.2 Noise Canceler Operation 8.3.7 Pin Functions The pin function is switched as shown below according to the combination of the PnDDR bit and the P3nNCE bit. P3nDDR 0 P3nNCE Pin function 1 0 1 x ExDBn input pin P3n input pin P3n output pin [Legend] n = 7 to 0 x: Don't care 8.3.8 Port 3 Input Pull-Up MOS Port 3 has a built-in input pull-up MOS that can be controlled by software.
Section 8 I/O Ports 8.4 Port 4 Port 4 is an 8-bit I/O port. Port 4 pins also function as external interrupt input and de-bounce input. Port 4 has the following registers. • Port 4 data direction register (P4DDR) • Port 4 data register (P4DR) • Port 4 pull-up MOS control register (P4PCR) • Noise canceler enable register (P4NCE) • Noise canceler mode control register (P4NCMC) • Noise cancel cycle setting register (NCCS) 8.4.
Section 8 I/O Ports 8.4.2 Port 4 Data Register (P4DR) P4DR stores output data for the port 4 pins. These bits are initialized only by a system reset, and retain their values even when an internal reset signal is generated by the WDT. Bit Bit Name Initial Value R/W Description 7 P47DR 0 6 P46DR 0 5 P45DR 0 4 P44DR 0 3 P43DR 0 R/W P4DR stores output data for the port 4 pins that are used as the general output port.
Section 8 I/O Ports 8.4.4 Noise Canceler Enable Register (P4NCE) P4NCE enables or disables the noise canceler circuit at port 4. Bit Bit Name Initial Value R/W Description 7 P47NCE 0 6 P46NCE 0 5 P45NCE 0 4 P44NCE 0 R/W When the noise canceler circuit is enabled, the pin state is fetched in the P4DR in the sampling cycle set by the R/W NCCS. R/W The operating state changes according to the other R/W control bits. Check the pin functions. All 0 R/W Reserved 3 to 0 ⎯ 8.4.
Section 8 I/O Ports 8.4.6 Noise Canceler Cycle Setting Register (NCCS) NCCS controls the sampling cycles of the noise cancelers. Bit Bit Name Initial Value R/W Description 7 to 3 ⎯ Undefined R/W Reserved 2 NCCK2 0 1 NCCK1 0 R/W These bits set the sampling cycle of the noise R/W cancelers. 0 NCCK0 0 The read value is undefined. R/W • When φ = 25 MHz 000: 80 ns φ/2 001: 1.28 μs φ/32 010: 20.48 μs φ/512 011: 327.7 μs φ/8192 100: 1.31 ms φ/32768 101: 2.62 ms φ/65536 110: 5.
Section 8 I/O Ports P4n input 1 expected P4nDR 0 expected P4nDR (n = 7 to 4) Figure 8.4 Noise Canceler Operation 8.4.7 Pin Functions The relationship between register setting values and pin functions are as follows. • P47 to P44 The pin function is switched as shown below according to the P4nDDR bit and P4nNCE bit. When the ISSn bit in ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQn input pin.
Section 8 I/O Ports • P43 to P40 The pin function is switched as shown below according to the P4nDDR bit. When the ISSn bit in ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQn input pin. To use this pin as the IRQn input pin, clear the P4nDDR bit to 0. P4nDDR Pin function 0 1 P4n input pin P4n output pin IRQn input pin [Legend] n = 3 to 0 8.4.
Section 8 I/O Ports 8.5 Port 5 Port 5 is a 4-bit I/O port. Port 5 pins also function as interrupt input, PWMX output, and SCI_1 input/output. Port 5 has the following registers. • Port 5 data direction register (P5DDR) • Port 5 data register (P5DR) 8.5.1 Port 5 Data Direction Register (P5DDR) The individual bits of P5DDR specify input or output for the pins of port 5.
Section 8 I/O Ports 8.5.2 Port 5 Data Register (P5DR) P5DR stores output data for the port 5 pins. Bit Bit Name Initial Value R/W Description 7 P57DR 0 R/W 6 P56DR Undefined* R P5DR stores output data for the port 5 pins that are used as the general output port. If a port 5 read is performed while the P5DDR bits are set to 1, the P5DR values are read. If a port 5 read is performed while the P5DDR bits are cleared to 0, the pin states are read.
Section 8 I/O Ports • P56/IRQ14/PWX0/φ/EXCL The pin function is switched as shown below according to the combination of the OEA bit in DACR of PWMX, the EXCLE bit in LPWRCR, and the P56DDR bit. When the ISS14 bit in ISSR16 is cleared to 0 and the IRQ14E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ14 input pin. To use this pin as the IRQ14 input pin, clear the P56DDR bit to 0.
Section 8 I/O Ports • P52/IRQ10/TxD1 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1, the SMIF bit in SCMR, and the P52DDR bit. When the ISS10 bit in ISSR16 is cleared to 0 and the IRQ10E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ10 input pin. To use this pin as the IRQ10 input pin, clear the P52DDR bit to 0.
Section 8 I/O Ports 8.6 Port 6 Port 6 is a 4-bit I/O port. Port 6 has the following registers. • Port 6 data direction register (P6DDR) • Port 6 data register (P6DR) • Port 6 pull-up MOS control register (P6PCR) 8.6.1 Port 6 Data Direction Register (P6DDR) The individual bits of P6DDR specify input or output for the pins of port 6.
Section 8 I/O Ports 8.6.2 Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved 6 ⎯ 0 R/W 5 ⎯ 0 R/W 4 ⎯ 0 R/W 3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W 0 P60DR 0 R/W 8.6.3 P6DR stores output data for the port 6 pins that are used as the general output port. If a port 6 read is performed while the P6DDR bits are set to 1, the P6DR values are read.
Section 8 I/O Ports 8.6.4 Port 6 Input Pull-Up MOS Port 6 has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used in single-chip mode. Table 8.6 summarizes the input pull-up MOS states. Table 8.6 Port 6 Input Pull-Up MOS States Reset Hardware Standby Mode Software Standby Mode In Other Operations Off Off On/Off On/Off [Legend] Off: Always off. On/Off: On when input state and P6PCR = 1: otherwise off. Rev. 3.00 Sep.
Section 8 I/O Ports 8.7 Port 7 Port 7 is an 8-bit input port. Port 7 pins also function as A/D converter analog input and interrupt input. Port 7 has the following register. • Port 7 input data register (P7PIN) 8.7.1 Port 7 Input Data Register (P7PIN) P7PIN indicates the pin states. Bit Bit Name Initial Value R/W Description 7 P77PIN Undefined* R 6 P76PIN Undefined* R When a P7PIN read is performed, the pin states are always read.
Section 8 I/O Ports 8.7.2 Pin Functions Each pin of port 7 can also be used as the interrupt input pins (ExIRQ0 to ExIRQ7) and analog input pins of the A/D converter (AN0 to AN7). By setting the ISS bit of the ISSR to 1, the pins can also be used as the interrupt input pin (ExIRQ0 to ExIRQ7). When the interrupt input pin is set, do not use the pins for the A/D converter.
Section 8 I/O Ports • P75/ExIRQ5/AN5 The pin function is switched as shown below according to the combination of the CH2 to CH0 bits in ADCSR of the A/D converter, the SCANE bit in ADCR, and the ISS5 bit in ISSR of the interrupt controller. Do not set these bits to other values than those shown in the following table.
Section 8 I/O Ports • P73/ExIRQ3/AN3 The pin function is switched as shown below according to the combination of the CH2 to CH0 bits in ADCSR of the A/D converter, the SCANE and SCANS bits in ADCR, and the ISS3 bit in ISSR of the interrupt controller. Do not set these bits to other values than those shown in the following table.
Section 8 I/O Ports • P71/ExIRQ1/AN1 The pin function is switched as shown below according to the combination of the CH2 to CH0 bits in ADCSR of the A/D converter, the SCANE and SCANS bits in ADCR, and the ISS1 bit in ISSR of the interrupt controller. Do not set these bits to other values than those shown in the following table.
Section 8 I/O Ports Table 8.
Section 8 I/O Ports 8.8 Port 8 Port 8 is an 8-bit I/O port. Port 8 pins also function as the A/D converter external trigger input, SCI_1 and SCI_3 input/output, IIC_0 and IIC_1 input/output, and interrupt input. Pins 83 to 80 perform the NMOS push-pull output. Port 8 has the following registers. • Port 8 data direction register (P8DDR) • Port 8 data register (P8DR) 8.8.1 Port 8 Data Direction Register (P8DDR) The individual bits of P8DDR specify input or output for the pins of port 8.
Section 8 I/O Ports 8.8.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Bit Name Initial Value R/W Description 7 P87DR 0 R/W 6 P86DR 0 R/W P8DR stores output data for the port 8 pins that are used as the general output port. 5 P85DR 0 R/W 4 P84DR 0 R/W 3 P83DR 0 R/W 2 P82DR 0 R/W 1 P81DR 0 R/W 0 P80DR 0 R/W 8.8.3 If a port 8 read is performed while the P8DDR bits are set to 1, the P8DR values are read.
Section 8 I/O Ports • P86/ExIRQ14/RxD3 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_3, the SMIF bit in SCMR, and the P86DDR bit. When the ISS14 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ14 input pin. To use this pin as the ExIRQ14 input pin, clear the P86DDR bit to 0.
Section 8 I/O Ports • P84/ExIRQ12/SCK3 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_3, the CKE1 and CKE0 bits in SCR, and the P84DDR bit. When the ISS12 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ12 input pin. To use this pin as the ExIRQ12 input pin, clear the P84DDR bit to 0.
Section 8 I/O Ports • P82/ExIRQ10/SCL1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_1 and the P82DDR bit. When the ISS10 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ10 input pin. To use this pin as the ExIRQ10 input pin, clear the P82DDR bit to 0. When this pin is used as the P82 output pin, the output format is NMOS push-pull output. The output format for SCL1 is NMOS open-drain output, and direct bus drive is possible.
Section 8 I/O Ports • P80/ExIRQ8/SCL0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0 and the P80DDR bit. When the ISS8 bit in ISSR16 is set to 1, this pin can be used as the ExIRQ8 input pin. To use this pin as the ExIRQ8 input pin, clear the P80DDR bit to 0. When this pin is used as the P80 output pin, the output format is NMOS push-pull output. The output format for SCL0 is NMOS open-drain output, and direct bus drive is possible.
Section 8 I/O Ports 8.9 Port A Port A is an 8-bit I/O port. Port A pins also function as event counter input. Pin functions are switched depending on the operating mode. Port A has the following registers. • Port A data direction register (PADDR) • Port A output data register (PAODR) • Port A input data register (PAPIN) 8.9.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A.
Section 8 I/O Ports 8.9.2 Port A Output Data Register (PAODR) PAODR stores output data for the port A pins. Bit Bit Name Initial Value R/W Description 7 PA7ODR 0 R/W 6 PA6ODR 0 R/W PAODR stores output data for the port A pins that are used as the general output port. 5 PA5ODR 0 R/W 4 PA4ODR 0 R/W 3 PA3ODR 0 R/W 2 PA2ODR 0 R/W 1 PA1ODR 0 R/W 0 PA0ODR 0 R/W 8.9.3 Port A Input Data Register (PAPIN) PAPIN indicates the pin states.
Section 8 I/O Ports 8.9.4 Pin Functions The relationship between the operating mode, register setting values, and pin functions are as follows. Port A functions as event counter input and also as an I/O port, and input or output can be specified in bit units. • PA7/EVENT7, PA6/EVENT6, PA5/EVENT5, PA4/EVENT4, PA3/EVENT3, PA2/EVENT2, PA1/EVENT1, PA0/EVENT0 The pin function is switched as shown below according to the PAnDDR bit.
Section 8 I/O Ports 8.9.5 Input Pull-Up MOS Port A has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis. PAnDDR 0 PAnODR PAn pull-up MOS 1 1 0 x ON OFF OFF [Legend] n = 7 to 0 x: Don't care The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.
Section 8 I/O Ports 8.10 Port C Port C is a 6-bit I/O port. Port C pins also function as PWMX output, and IIC_2 and IIC_3 input/output. The output format of ports C0 to C3 is NMOS push-pull output. Port C has the following registers. • Port C data direction register (PCDDR) • Port C output data register (PCODR) • Port C input data register (PCPIN) 8.10.1 Port C Data Direction Register (PCDDR) PCDDR is used to specify the input/output attribute of each pin of port C.
Section 8 I/O Ports 8.10.2 Port C Output Data Register (PCODR) PCODR stores output data for port C. Bit Bit Name Initial Value R/W Description 7 PC7ODR 0 R/W 6 PC6ODR 0 R/W The PCODR register stores the output data for the pins that are used as a general output port. 5 ⎯ 0 R/W 4 ⎯ 0 R/W 3 PC3ODR 0 R/W 2 PC2ODR 0 R/W 1 PC1ODR 0 R/W 0 PC0ODR 0 R/W 8.10.3 Bits 5 and 4 are reserved. Port C Input Data Register (PCPIN) PCPIN indicates the pin states of port C.
Section 8 I/O Ports 8.10.4 Pin Functions Port C functions as IIC_2 and IIC_3 input/output, and PWMX output. The relationship between register setting values and pin functions are as follows. • PC7/PWX3 The pin function is switched as shown below according to the combination of the OEB bit in DACR of the 14-bit PWMX and the PC7DDR bit.
Section 8 I/O Ports • PC2/SCL3 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_3 and the PC2DDR bit. ICE PC2DDR Pin function 0 1 0 1 x PC2 input pin PC2 output pin SCL3 input/output pin [Legend] x: Don't care • PC1/SDA2 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_2 and the PC1DDR bit.
Section 8 I/O Ports 8.11 Port E Port E is an 8-bit I/O port. Port E pins also function as LPC input/output. Port E has the following registers. • Port E data direction register (PEDDR) • Port E output data register (PEODR) • Port E input data register (PEPIN) 8.11.1 Port E Data Direction Register (PEDDR) PEDDR is used to specify the input/output attribute of each pin of port E.
Section 8 I/O Ports 8.11.2 Port E Output Data Register (PEODR) PEODR stores output data for the port E pins. Bit Bit Name Initial Value R/W Description 7 PE7ODR 0 R/W 6 PE6ODR 0 R/W The PEODR register stores the output data for the pins that are used a general output port. 5 PE5ODR 0 R/W 4 PE4ODR 0 R/W 3 PE3ODR 0 R/W 2 PE2ODR 0 R/W 1 PE1ODR 0 R/W 0 PE0ODR 0 R/W 8.11.3 Port E Input Data Register (PEPIN) PEPIN indicates the pin states of port E.
Section 8 I/O Ports 8.11.4 Pin Functions Port E also functions as LPC input/output. The pin function is switched with LPC enabled or disabled. The LPC module is disabled when the LPC1E, LPC2E, and LPC3E bits in HICR0 of LPC are all 0. • PE7/SERIRQ The pin function is switched as shown below according to the LPC enabled/disabled and the PE7DDR bit.
Section 8 I/O Ports • PE4/LFRAME The pin function is switched as shown below according to the LPC enabled/disabled and the PE4DDR bit. LPC PE4DDR Pin function Disabled Enabled 0 1 x PE4 input pin PE4 output pin LFRAME input pin [Legend] x: Don't care • PE3/LAD3 The pin function is switched as shown below according to the LPC enabled/disabled and the PE3DDR bit.
Section 8 I/O Ports • PE1/LAD1 The pin function is switched as shown below according to the LPC enabled/disabled and the PE1DDR bit. LPC PE1DDR Pin function Disabled Enabled 0 1 x PE1 input pin PE1 output pin LAD1 input/output pin [Legend] x: Don't care • PE0/LAD0 The pin function is switched as shown below according to the LPC enabled/disabled and the PE0DDR bit. LPC PE0DDR Pin function Disabled 0 1 x PE0 input pin PE0 output pin LAD0 input/output pin [Legend] x: Don't care Rev. 3.
Section 8 I/O Ports 8.12 Change of Peripheral Function Pins I/O ports that also function as peripheral modules, such as the external interrupt pins, can be changed. I/O ports that also function as the external interrupt pins are changed according to the setting of ISSR16 and ISSR. I/O ports that also function as the 8-bit timer input pins are changed according to the setting of PTCNT0. The pin name of the peripheral function is indicated by adding ‘Ex’ at the head of the original pin name.
Section 8 I/O Ports • ISSR Bit Bit Name Initial Value R/W Description 7 ISS7 0 R/W 0: P47/IRQ7 is selected 1: P77/ExIRQ7 is selected 6 ISS6 0 R/W 0: P46/IRQ6 is selected 1: P76/ExIRQ6 is selected 5 ISS5 0 R/W 0: P45/IRQ5 is selected 1: P75/ExIRQ5 is selected 4 ISS4 0 R/W 0: P44/IRQ4 is selected 1: P74/ExIRQ4 is selected 3 ISS3 0 R/W 0: P43/IRQ3 is selected 1: P73/ExIRQ3 is selected 2 ISS2 0 R/W 0: P42/IRQ2 is selected 1: P72/ExIRQ2 is selected 1 ISS1 0 R/W 0 ISS0 0
Section 9 14-Bit PWM Timer (PWMX) Section 9 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with four output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. 9.1 Features • Division of pulse into multiple base cycles to reduce ripple • Eight resolution settings The resolution can be set to 1, 2, 64, 128, 256, 1024, 4096, or 16384 system clock cycles.
Section 9 14-Bit PWM Timer (PWMX) 9.2 Input/Output Pins Table 9.1 lists the PWMX (D/A) module input and output pins. Table 9.1 Pin Configuration Name Abbreviation I/O Function PWMX output pin 0 PWX0 Output PWM timer pulse output of PWMX_0 channel A PWMX output pin 1 PWX1 Output PWM timer pulse output of PWMX_0 channel B PWMX output pin 2 PWX2 Output PWM timer pulse output of PWMX_1 channel A PWMX output pin 3 PWX3 Output PWM timer pulse output of PWMX_1 channel B 9.
Section 9 14-Bit PWM Timer (PWMX) 9.3.1 PWMX (D/A) Counter (DACNT) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper two bits. DACNT cannot be accessed in 8-bit units. DACNT should always be accessed in 16-bit units.
Section 9 14-Bit PWM Timer (PWMX) 9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. The DADR registers cannot be accessed in 8-bit units. The DADR registers should always be accessed in 16-bit units. For details, see section 9.4, Bus Master Interface.
Section 9 14-Bit PWM Timer (PWMX) • DADRB Bit Bit Name Initial Value 15 to 2 DA13 to DA0 All 1 R/W Description R/W D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution.
Section 9 14-Bit PWM Timer (PWMX) 9.3.3 PWMX (D/A) Control Register (DACR) DACR enables the PWM outputs, and selects the output phase and operating speed. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved 6 PWME 0 R/W The initial value should not be changed. PWMX Enable Starts or stops the PWM D/A counter (DACNT). 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H'0003 5, 4 ⎯ All 1 R Reserved These bits are always read as 1 and cannot be modified.
Section 9 14-Bit PWM Timer (PWMX) 9.3.4 Peripheral Clock Select Register (PCSR) PCSR and the CKS bit of DACR select the operating speed. Bit Bit Name Initial Value R/W Description 7 PWCKX1B 0 R/W PWMX_1 Clock Select 6 PWCKX1A 0 R/W These bits select a clock cycle with the CKS bit of DACR of PWMX_1 being 1. See table 9.2. 5 PWCKX0B 0 R/W PWMX_0 Clock Select 4 PWCKX0A 0 R/W These bits select a clock cycle with the CKS bit of DACR of PWMX_0 being 1. See table 9.2.
Section 9 14-Bit PWM Timer (PWMX) 9.4 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and read from as follows. • Write When the upper byte is written to, the upper-byte write data is stored in TEMP.
Section 9 14-Bit PWM Timer (PWMX) 9.5 Operation A PWM waveform like the one shown in figure 9.2 is output from the PWX pin. DA13 to DA0 in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and DA13 to DA0 in DADR value corresponds to the total width (TH) of the high (1) output pulses. Figures 9.3 and 9.
Section 9 14-Bit PWM Timer (PWMX) Settings and Operation (Examples when φ = 25 MHz) Table 9.3 PCSR Fixed DADR Bits Reso- PWCKX0 lution PWCKX1 Conver- T Base B A CKS (μs) CFS Cycle ⎯ ⎯ ⎯ 0 0 C 0.04 2.56 μs/ Bit Data sion TL/TH Accuracy Cycle (OS = 0/OS = 1) (Bits) 655.36 μs Always low/high output DA13 to 0 = H'0000 to H'00FF 390.6 kHz (Data value) × T DA13 to 0 = H'0100 to H'3FFF 1 10.24 μs/ 655.36 μs Always low/high output DA13 to 0 = H'0000 to H'003F 97.
Section 9 14-Bit PWM Timer (PWMX) PCSR Fixed DADR Bits Reso- PWCKX0 lution PWCKX1 Conver- T Base C B A CKS (μs) CFS Cycle 0 1 1 1 0 10.24 655.4 μs/ sion Cycle Bit Data TL/TH Accuracy (OS = 0/OS = 1) (Bits) 167.77 ms Always low/high output 14 DA13 to 0 = H'0000 to H'00FF 1.5 kHz (Data value) × T DA13 to 0 = H'0100 to H'3FFF 1 2621.4 μs/ 167.77 ms Always low/high output (Data value) × T (φ/256) 1 0 0 1 40.96 DA13 to 0 = H'0040 to H'3FFF 0 2.62 ms/ 671.
Section 9 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tL1 tf2 tf255 tL2 tL3 tL255 tf256 tL256 tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64 tL1 + tL2 + tL3+ ··· + tL255 + tL256 = TL a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tL1 tf2 tL2 tf63 tL3 tL63 tf64 tL64 tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256 tL1 + tL2 + tL3 + ··· + tL63 + tL64 = TL b. CFS = 1 [base cycle = resolution (T) × 256] Figure 9.3 Output Waveform (OS = 0, DADR corresponds to TL) Rev. 3.
Section 9 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tH1 tf2 tf255 tH2 tH3 tf256 tH255 tH256 tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64 tH1 + tH2 + tH3 + ··· + tH255 + tH256 = TH a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tH1 tf2 tf63 tH2 tH3 tf64 tH63 tH64 tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256 tH1 + tH2 + tH3 + ··· + tH63 + tH64 = TH b. CFS = 1 [base cycle = resolution (T) × 256] Figure 9.
Section 9 14-Bit PWM Timer (PWMX) Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the location of base pulse No. 63 according to table 9.4. Thus, an additional pulse of 1/256 × (T) is to be added to the base pulse. 1 conversion cycle Base cycle No. 0 Base cycle Base cycle No. 1 No. 63 Base pulse High width: 2/256 × (T) Additional pulse output location Base pulse 2/256 × (T) Additional pulse 1/256 × (T) Figure 9.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Lower 6 bits 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0
Section 9 14-Bit PWM Timer (PWMX) Rev. 3.00 Sep.
Section 10 16-Bit Free-Running Timer (FRT) Section 10 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT). 10.1 Features • Selection of four clock sources ⎯ One of the three internal clocks (φ/2, φ/8, or φ/32) can be selected. • Two independent comparators • Counter clearing ⎯ The free-running counters can be cleared on compare-match A. • Three independent interrupts ⎯ Two compare-match interrupts and one overflow interrupt can be requested independently. Rev. 3.
Section 10 16-Bit Free-Running Timer (FRT) Figure 10.1 shows a block diagram of the FRT.
Section 10 16-Bit Free-Running Timer (FRT) 10.2 Register Descriptions The FRT has the following registers. • Free-running counter (FRC) • Output compare register A (OCRA) • Output compare register B (OCRB) • Output compare register AR (OCRAR) • Output compare register AF (OCRAF) • Timer interrupt enable register (TIER) • Timer control/status register (TCSR) • Timer control register (TCR) • Timer output compare control register (TOCR) Note: OCRA and OCRB share the same address.
Section 10 16-Bit Free-Running Timer (FRT) 10.2.3 Output Compare Registers AR and AF (OCRAR and OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. They are accessed when the ICRS bit in TOCR is set to 1. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA.
Section 10 16-Bit Free-Running Timer (FRT) 10.2.4 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit Bit Name Initial Value R/W 7 to 4 ⎯ All 0 R Description Reserved These bits are always read as 0 and cannot be modified. 3 OCIAE 0 R/W Output Compare Interrupt A Enable Selects whether to enable output compare interrupt A request (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.
Section 10 16-Bit Free-Running Timer (FRT) 10.2.5 Timer Control/Status Register (TCSR) TCSR is used for counter clear selection and control of interrupt request signals. Bit Bit Name Initial Value R/W 7 to 4 ⎯ All 0 R Description Reserved These bits are always read as 0 and cannot be modified. 3 OCFA 0 R/(W)* Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value.
Section 10 16-Bit Free-Running Timer (FRT) 10.2.6 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. Bit Bit Name Initial Value R/W Description 7 to 2 ⎯ All 0 R Reserved 1 CKS1 0 R/W Clock Select 1 and 0 0 CKS0 0 R/W Select clock source for FRC. These bits are always read as 0 and cannot be modified.
Section 10 16-Bit Free-Running Timer (FRT) 10.2.7 Timer Output Compare Control Register (TOCR) TOCR enables output from the output compare pins, selects the output levels, switches access between output compare registers A and B, and controls the OCRA operating modes. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R Reserved 6 OCRAMS 0 R/W Output Compare A Mode Select This bit is always read as 0 and cannot be modified.
Section 10 16-Bit Free-Running Timer (FRT) 10.3 Operation Timing 10.3.1 FRC Increment Timing Figure 10.2 shows the FRC increment timing with an internal clock source. φ Internal clock FRC input clock FRC N–1 N N+1 Figure 10.2 Increment Timing with Internal Clock Source 10.3.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value).
Section 10 16-Bit Free-Running Timer (FRT) 10.3.3 FRC Clear Timing FRC can be cleared when compare-match A occurs. Figure 10.4 shows the timing of this operation. φ Compare-match A signal FRC N H'0000 Figure 10.4 Clearing of FRC by Compare-Match A Signal 10.3.4 Timing of Output Compare Flag (OCF) Setting The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when the FRC value matches the OCRA or OCRB value.
Section 10 16-Bit Free-Running Timer (FRT) 10.3.5 Timing of FRC Overflow Flag (OVF) Setting The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 10.6 shows the timing of setting the OVF flag. φ FRC H'FFFF H'0000 Overflow signal OVF Figure 10.6 Timing of Overflow Flag (OVF) Setting Rev. 3.00 Sep.
Section 10 16-Bit Free-Running Timer (FRT) 10.3.6 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed. Figure 10.7 shows the OCRA write timing. φ FRC N N +1 OCRA N N+A OCRAR, OCRAF A Compare-match signal Figure 10.7 OCRA Automatic Addition Timing 10.
Section 10 16-Bit Free-Running Timer (FRT) 10.5 Usage Notes 10.5.1 Conflict between FRC Write and Clear If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 10.8 shows the timing for this type of conflict. Write cycle of FRC T1 T2 φ Address FRC address Internal write signal Counter clear signal FRC N H'0000 Figure 10.8 Conflict between FRC Write and Clear Rev. 3.00 Sep.
Section 10 16-Bit Free-Running Timer (FRT) 10.5.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 10.9 shows the timing for this type of conflict. Write cycle of FRC T1 T2 φ Address FRC address Internal write signal FRC input clock FRC N M Write data Figure 10.9 Conflict between FRC Write and Increment Rev. 3.00 Sep.
Section 10 16-Bit Free-Running Timer (FRT) 10.5.3 Conflict between OCR Write and Compare-Match If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 10.10 shows the timing for this type of conflict.
Section 10 16-Bit Free-Running Timer (FRT) φ Address OCRAR (OCRAF) address Internal write signal OCRAR (OCRAF) Compare-match signal Old data New data Disabled FRC N OCR N N+1 Automatic addition is not performed because compare-match signals are disabled. Figure 10.11 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Used) 10.5.4 Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may source FRC to increment.
Section 10 16-Bit Free-Running Timer (FRT) Table 10.2 Switching of Internal Clock and FRC Operation No.
Section 10 16-Bit Free-Running Timer (FRT) No. 4 Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to high FRC Operation Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. Rev. 3.00 Sep.
Section 11 8-Bit Timer (TMR) Section 11 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0 and TMR_1) with two channels operating on the basis of an 8-bit counter. This LSI also has two channels of similar 8-bit timer modules (TMR_Y and TMR_X). 11.1 Features • Selection of clock sources ⎯ TMR_0, TMR_1: The counter input clock can be selected from six internal clocks. ⎯ TMR_Y, TMR_X: The counter input clock can be selected from three internal clocks.
Section 11 8-Bit Timer (TMR) Figures 11.1 and 11.2 show block diagrams of 8-bit timers.
Section 11 8-Bit Timer (TMR) Internal clock TMR_X φ, φ/2, φ/4 TMR_Y φ/4, φ/256, φ/2048 Clock X Clock Y Select clock Compare match AX Compare match AY TCORA_Y TCORA1_X Comparator A_Y Comparator A_X TCNT_Y TCNT_X Overflow X Overflow Y Clear Y Control logic Compare match BX Compare match BY Internal bus Clear X Comparator B_Y Comparator B_X TCORB_Y TCORB_X TCOR_Y TCSR_X TCR_Y TCR_X Interrupt signals [Legend] TCORA_Y: TCORB_Y: TCNT_Y: TCSR_Y: TCR_Y: CMIAX CMIBX OVIX CMIAY CMIBY OVIY Ti
Section 11 8-Bit Timer (TMR) 11.2 Register Descriptions The TMR has the following registers for each channel. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). • Timer counter (TCNT) • Time constant register A (TCORA) • Time constant register B (TCORB) • Timer control register (TCR) • Timer control/status register (TCSR) • Timer connection register S (TCONRS)* Notes: Some of the registers of TMR_X and TMR_Y use the same address.
Section 11 8-Bit Timer (TMR) 11.2.2 Time Constant Register A (TCORA) TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle. TCORA is initialized to H'FF.
Section 11 8-Bit Timer (TMR) 11.2.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. TCR_Y can be accessed when the TMRX/Y bit in TCONRS is 1. TCR_X can be accessed when the TMRX/Y bit in TCONRS is 0. See section 11.2.6, Timer Connection Register S (TCONRS).
Section 11 8-Bit Timer (TMR) Table 11.
Section 11 8-Bit Timer (TMR) Table 11.
Section 11 8-Bit Timer (TMR) 11.2.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. About the TCSR_Y and TCSR_X accesses see section 11.2.6, Timer Connection Register S (TCONRS).
Section 11 8-Bit Timer (TMR) • TCSR_1 Bit Bit Name Initial Value R/W 7 CMFB 0 R/(W)* Compare-Match Flag B Description [Setting condition] When the values of TCNT_1 and TCORB_1 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 6 CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_1 and TCORA_1 match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT_1 overflows f
Section 11 8-Bit Timer (TMR) • TCSR_Y This register can be accessed when the TMRX/Y bit in TCONRS is 1.
Section 11 8-Bit Timer (TMR) • TCSR_X This register can be accessed when the TMRX/Y bit in TCONRS is 0.
Section 11 8-Bit Timer (TMR) 11.2.6 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMR_X or TMR_Y registers. Bit Bit Name Initial Value R/W Description 7 TMRX/Y 0 R/W TMR_X/TMR_Y Access Select For details, see table 11.2. 0: The TMR_X registers are accessed at addresses H'FFFFF0 to H'FFFFF5 1: The TMR_Y registers are accessed at addresses H'FFFFF0 to H'FFFFF5 6 to 0 ⎯ All 0 R/W Reserved The initial values should not be changed. Table 11.
Section 11 8-Bit Timer (TMR) 11.3 Operation Timing 11.3.1 TCNT Count Timing Figure 11.3 shows the TCNT count timing with an internal clock source. φ Internal clock TCNT input clock TCNT N–1 N Figure 11.3 Count Timing for Internal Clock Input Rev. 3.00 Sep.
Section 11 8-Bit Timer (TMR) 11.3.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR match, the compare-match signal is not generated until the next TCNT input clock. Figure 11.4 shows the timing of CMF flag setting.
Section 11 8-Bit Timer (TMR) 11.3.4 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 11.6 shows the timing of OVF flag setting. φ TCNT H'FF H'00 Overflow signal OVF Figure 11.6 Timing of OVF Flag Setting Rev. 3.00 Sep.
Section 11 8-Bit Timer (TMR) 11.4 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected. 11.4.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with TMR_0 occupying the upper eight bits and TMR_1 occupying the lower eight bits.
Section 11 8-Bit Timer (TMR) 11.5 Interrupt Sources TMR_0, TMR_1, TMR_Y and TMR_X can generate three types of interrupts: CMIA, CMIB, and OVI. Table 11.3 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. The CMIA and CMIB interrupts can be used as DTC activation interrupt sources. Table 11.
Section 11 8-Bit Timer (TMR) 11.6 Usage Notes 11.6.1 Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 11.7, the counter clear takes priority and the write is not performed. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 11.7 Conflict between TCNT Write and Counter Clear Rev. 3.00 Sep.
Section 11 8-Bit Timer (TMR) 11.6.2 Conflict between TCNT Write and Increment If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure 11.8, the write takes priority and the counter is not incremented. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 11.8 Conflict between TCNT Write and Increment Rev. 3.00 Sep.
Section 11 8-Bit Timer (TMR) 11.6.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 11.9, the TCOR write takes priority and the compare-match signal is disabled. TCOR write cycle by CPU T1 T2 φ Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare-match signal Disabled Figure 11.9 Conflict between TCOR Write and Compare-Match Rev. 3.00 Sep.
Section 11 8-Bit Timer (TMR) 11.6.4 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 11.4 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no.
Section 11 8-Bit Timer (TMR) No.
Section 11 8-Bit Timer (TMR) 11.6.5 Mode Setting with Cascaded Connection If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1 are not generated, and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided. Rev. 3.00 Sep.
Section 12 Watchdog Timer (WDT) Section 12 Watchdog Timer (WDT) This LSI has two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can output an overflow signal (RESO) externally if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can generate an internal reset signal or an internal NMI interrupt signal. When this watchdog function is not needed, the WDT can be used as an interval timer.
Section 12 Watchdog Timer (WDT) Internal NMI (Interrupt request signal*2) Interrupt control Overflow Clock Clock selection Reset control RESO signal*1 Internal reset signal*1 TCNT_0 φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock Internal bus WOVI0 (Interrupt request signal) TCSR_0 Bus interface Module bus WDT_0 Internal NMI (Interrupt request signal*2) RESO signal*1 Interrupt control Overflow Clock φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Clock selection
Section 12 Watchdog Timer (WDT) 12.2 Input/Output Pins The WDT has the pins listed in table 12.1. Table 12.1 Pin Configuration Name Symbol I/O Function Reset output pin RESO Output Outputs the counter overflow signal in watchdog timer mode Input Inputs the clock pulses to the WDT_1 prescaler counter External sub-clock input EXCL pin 12.3 Register Descriptions The WDT has the following registers.
Section 12 Watchdog Timer (WDT) 12.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. • TCSR_0 Bit Bit Name Initial Value R/W 7 OVF 0 R/(W)* Overflow Flag Description Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting conditions] • When TCNT overflows (changes from H'FF to H'00) • When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Section 12 Watchdog Timer (WDT) Bit Bit Name 2 to 0 CKS2 to CKS0 Initial Value R/W Description All 0 R/W Clock Select 2 to 0 Select the clock to be input to TCNT. The overflow period for φ = 25 MHz is enclosed in parentheses. 000: φ/2 (frequency: 20.48 μs) 001: φ/64 (frequency: 655.36 μs) 010: φ/128 (frequency: 1.311 ms) 011: φ/512 (frequency: 5.243 ms) 100: φ/2048 (frequency: 20.97 ms) 101: φ/8192 (frequency: 83.89 ms) 110: φ/32768 (frequency: 335.5 ms) 111: φ/131072 (frequency: 1.
Section 12 Watchdog Timer (WDT) • TCSR_1 Bit 7 Bit Name OVF Initial Value 0 R/W Description 1 R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting conditions] • When TCNT overflows (changes from H'FF to H'00) • When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Section 12 Watchdog Timer (WDT) Bit Bit Name 2 to 0 CKS2 to CKS0 Initial Value R/W Description All 0 R/W Clock Select 2 to 0 Select the clock to be input to TCNT. The overflow period for φ = 25 MHz and φSUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: φ/2 (frequency: 20.48 μs) 001: φ/64 (frequency: 655.36 μs) 010: φ/128 (frequency: 1.311 ms) 011: φ/512 (frequency: 5.243 ms) 100: φ/2048 (frequency: 20.97 ms) 101: φ/8192 (frequency: 83.89 ms) 110: φ/32768 (frequency: 335.
Section 12 Watchdog Timer (WDT) 12.4 Operation 12.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally.
Section 12 Watchdog Timer (WDT) TCNT value Overflow H'FF Time H'00 WT/IT = 1 TME = 1 OVF = 1* Write H'00 to TCNT WT/IT = 1 Write H'00 to TME = 1 TCNT Internal reset signal 518 system clocks WT/IT: TME: OVF: Timer mode select bit Timer enable bit Overflow flag Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset. The XRST bit is also cleared to 0. Figure 12.2 Watchdog Timer Mode (RST/NMI = 1) Operation 12.4.
Section 12 Watchdog Timer (WDT) φ TCNT H'FF Overflow signal (internal signal) OVF Figure 12.4 OVF Flag Set Timing Rev. 3.00 Sep.
Section 12 Watchdog Timer (WDT) RESO Signal Output Timing 12.4.3 When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time, the low level signal is output from the RESO pin. The timing is shown in figure 12.5. φ TCNT H'FF H'00 Overflow signal (internal signal) OVF RESO signal Internal reset signal 132 states 518 states Figure 12.
Section 12 Watchdog Timer (WDT) 12.5 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is generated by an overflow Table 12.
Section 12 Watchdog Timer (WDT) 12.6 Usage Notes 12.6.1 Notes on Register Access The watchdog timer’s registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. Writing to TCNT and TCSR (Example of WDT_0): These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address.
Section 12 Watchdog Timer (WDT) 12.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 12.7 shows this operation. TCNT write cycle T1 T2 φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.7 Conflict between TCNT Write and Increment 12.6.
Section 12 Watchdog Timer (WDT) 12.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from/to watchdog timer to/from interval timer, while the WDT is operating, errors could occur in the operation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 12.6.
Section 12 Watchdog Timer (WDT) Rev. 3.00 Sep.
Section 13 Serial Communication Interface (SCI) Section 13 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clock synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Section 13 Serial Communication Interface (SCI) Asynchronous Mode: • Data length: 7 or 8 bits • Stop bit length: 1 or 2 bits • Parity: Even, odd, or none • Receive error detection: Parity, overrun, and framing errors • Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error Clock Synchronous Mode: • Data length: 8 bits • Receive error detection: Overrun errors Smart Card Interface: • An error signal can be automatically transmitted on detection of a parity er
Section 13 Serial Communication Interface (SCI) Module data bus RDR TDR BRR SCMR SSR φ SCR RxD1/RxD3 RSR TSR Baud rate generator SMR φ/4 φ/16 Transmission/ reception control TxD1/TxD3 Parity generation Internal data bus Bus interface Figure 13.1 shows a block diagram of SCI_1 and SCI_3.
Section 13 Serial Communication Interface (SCI) 13.2 Input/Output Pins Table 13.1 shows the input/output pins for each SCI channel. Table 13.
Section 13 Serial Communication Interface (SCI) 13.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 13.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data.
Section 13 Serial Communication Interface (SCI) 13.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode.
Section 13 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 1 and 0 0 CKS0 0 R/W These bits select the clock source for the baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 13.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 13.3.
Section 13 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 3 BCP1 0 R/W Basic Clock Pulse 1 and 0 2 BCP0 0 R/W These bits select the number of basic clock cycles in a 1bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 13.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 13.3.
Section 13 Serial Communication Interface (SCI) 13.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, see section 13.8, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode.
Section 13 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 1 and 0 0 CKE0 0 R/W These bits select the clock source and SCK pin function. Asynchronous mode: 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1x: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.
Section 13 Serial Communication Interface (SCI) • Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit Bit Name Initial Value R/W 7 TIE 0 R/W Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled.
Section 13 Serial Communication Interface (SCI) 13.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode.
Section 13 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W 5 ORER 0 R/(W)* Overrun Error Description [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 4 FER 0 R/(W)* Framing Error [Setting condition] When the stop bit is 0 [Clearing condition] When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked.
Section 13 Serial Communication Interface (SCI) • Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit 7 Bit Name TDRE Initial Value 1 R/W Description 1 R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR, and TDR can be written to.
Section 13 Serial Communication Interface (SCI) Bit 3 Bit Name PER Initial Value 0 R/W Description 1 R/(W)* Parity Error [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1 2 TEND 1 R Transmit End TEND is set to 1 when the receiving end acknowledges no error signal and the next transmit data is ready to be transferred to TDR.
Section 13 Serial Communication Interface (SCI) 13.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ All 1 R Reserved These bits are always read as 1 and cannot be modified. 3 SDIR 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Stores receive data as LSB first in RDR.
Section 13 Serial Communication Interface (SCI) 13.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 13.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clock synchronous mode, and smart card interface mode.
Section 13 Serial Communication Interface (SCI) Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ (MHz) 20 25 Bit Rate (bit/s) n N Error (%) n N Error (%) 110 3 88 –0.25 3 110 –0.02 150 3 64 0.16 3 80 –0.47 300 2 129 0.16 2 162 0.15 600 2 64 0.16 2 80 –0.47 1200 1 129 0.16 1 162 0.15 2400 1 64 0.16 1 80 –0.47 4800 0 129 0.16 0 162 0.15 9600 0 64 0.16 0 80 –0.47 19200 0 32 –1.36 0 40 –0.
Section 13 Serial Communication Interface (SCI) Table 13.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) 20 24 n N n N 500 ⎯ ⎯ ⎯ ⎯ 1k ⎯ ⎯ ⎯ ⎯ 2.5k 2 124 2 149 5k 1 249 2 74 10k 1 124 1 149 25k 0 199 0 239 50k 0 99 0 119 100k 0 49 0 59 250k 0 19 0 23 500k 0 9 0 11 1M 0 4 0 5 2.5M 0 1 5M 0 0* 110 250 [Legend] ⎯: Can be set, but there will be a degree of error.
Section 13 Serial Communication Interface (SCI) Table 13.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372) Operating Frequency φ (MHz) Bit Rate 20.00 21.4272 25 (bit/s) n N Error (%) n N Error (%) n N Error (%) 9600 0 2 -6.65 0 2 0.00 0 3 -12.49 Table 13.9 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372) φ (MHz) Maximum Bit Rate (bit/s) n N 20.00 26882 0 0 21.4272 28800 0 0 25.00 33602 0 0 Rev. 3.00 Sep.
Section 13 Serial Communication Interface (SCI) 13.4 Operation in Asynchronous Mode Figure 13.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
Section 13 Serial Communication Interface (SCI) 13.4.1 Data Transfer Format Table 13.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 13.5, Multiprocessor Communication Function. Table 13.
Section 13 Serial Communication Interface (SCI) 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Section 13 Serial Communication Interface (SCI) 13.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin.
Section 13 Serial Communication Interface (SCI) 13.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 13.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1.
Section 13 Serial Communication Interface (SCI) 13.4.5 Serial Data Transmission (Asynchronous Mode) Figure 13.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Section 13 Serial Communication Interface (SCI) Initialization [1] Start transmission [2] Read TDRE flag in SSR [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 13 Serial Communication Interface (SCI) 13.4.6 Serial Data Reception (Asynchronous Mode) Figure 13.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 13 Serial Communication Interface (SCI) Table 13.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.9 shows a sample flowchart for serial data reception. Table 13.
Section 13 Serial Communication Interface (SCI) Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER ∨ FER ∨ ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0.
Section 13 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 13.9 Sample Serial Reception Flowchart (2) Rev. 3.00 Sep.
Section 13 Serial Communication Interface (SCI) 13.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
Section 13 Serial Communication Interface (SCI) Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 13.
Section 13 Serial Communication Interface (SCI) 13.5.1 Multiprocessor Serial Data Transmission Figure 13.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
Section 13 Serial Communication Interface (SCI) 13.5.2 Multiprocessor Serial Data Reception Figure 13.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 13.
Section 13 Serial Communication Interface (SCI) 1 Start bit 0 Data (ID1) MPB D0 D1 D7 1 Stop bit Start bit 1 0 Data (Data 1) D0 D1 Stop MPB bit D7 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated If not this station’s ID, MPIE bit is set to 1 again RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine RXI interrupt request is not generated, and RDR retains its state (a) Data does not match
Section 13 Serial Communication Interface (SCI) Initialization [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [1] Start reception Set MPIE bit in SCR to 1 [2] ID reception cycle: Set the MPIE bit in SCR to 1. [2] [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID.
Section 13 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.00 Sep.
Section 13 Serial Communication Interface (SCI) 13.6 Operation in Clock Synchronous Mode Figure 13.14 shows the general format for clock synchronous communication. In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next.
Section 13 Serial Communication Interface (SCI) 13.6.2 SCI Initialization (Clock Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 13.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1.
Section 13 Serial Communication Interface (SCI) 13.6.3 Serial Data Transmission (Clock Synchronous Mode) Figure 13.16 shows an example of SCI operation for transmission in clock synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Section 13 Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 13.16 Sample SCI Transmission Operation in Clock Synchronous Mode Rev. 3.00 Sep.
Section 13 Serial Communication Interface (SCI) Initialization [1] Start transmission [2] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 13 Serial Communication Interface (SCI) 13.6.4 Serial Data Reception (Clock Synchronous Mode) Figure 13.18 shows an example of SCI operation for reception in clock synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2.
Section 13 Serial Communication Interface (SCI) [1] Initialization Start reception [2] Read ORER flag in SSR Yes ORER = 1 [3] No Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
Section 13 Serial Communication Interface (SCI) 13.6.5 Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode) Figure 13.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Section 13 Serial Communication Interface (SCI) Initialization [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 13 Serial Communication Interface (SCI) 13.7 Smart Card Interface Description The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification Card) standard as an enhanced serial communication interface function. Smart card interface mode can be selected using the appropriate register. 13.7.1 Sample Connection Figure 13.21 shows a sample connection between the smart card and this LSI. This LSI communicates with the IC card using a single transmission line.
Section 13 Serial Communication Interface (SCI) In normal transmission/reception Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp D7 Dp Output from the transmitting station When a parity error is generated Ds D0 D1 D2 D3 D4 D5 D6 DE Output from the transmitting station Output from the receiving station [Legend] Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 13.
Section 13 Serial Communication Interface (SCI) For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 13.24. Therefore, data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR.
Section 13 Serial Communication Interface (SCI) 13.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the internal baud rate generator can be used as a communication clock in smart card interface mode. In this mode, the SCI can operate using a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 settings (the frequency is always 16 times the bit rate in normal asynchronous mode).
Section 13 Serial Communication Interface (SCI) 372 clock cycles 186 clock cycles 0 185 185 371 0 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) 13.7.5 Initialization Before starting transmitting and receiving data, initialize the SCI using the following procedure.
Section 13 Serial Communication Interface (SCI) completion can be verified by reading the RDRF flag or PER and ORER flags. To switch from transmission to reception, first verify that transmission has completed, and initialize the SCI. At the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission completion can be verified by reading the TEND flag. 13.7.
Section 13 Serial Communication Interface (SCI) (n + 1) th transfer frame Retransfer frame nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer from TDR to TSR Transfer from TDR to TSR Transfer from TDR to TSR TEND [2] [3] FER/ERS [1] [3] Figure 13.26 Data Re-transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR, which is shown in figure 13.27.
Section 13 Serial Communication Interface (SCI) Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit in SCR to 0 End Figure 13.28 Sample Transmission Flowchart Rev. 3.00 Sep.
Section 13 Serial Communication Interface (SCI) 13.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is identical to that in normal serial communication interface mode. Figure 13.29 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1.
Section 13 Serial Communication Interface (SCI) Start Initialization Start reception ORER = 0 and PER = 0? No Yes Error processing No RDRF = 1? Yes Read data from RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Figure 13.30 Sample Reception Flowchart 13.7.8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 13.
Section 13 Serial Communication Interface (SCI) CKE0 SCK Specified pulse width Specified pulse width Figure 13.31 Clock Output Fixing Timing At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty ratio. At Power-On: To secure the appropriate clock duty ratio simultaneously with power-on, use the following procedure. 1. Initially, port input is enabled in the high-impedance state.
Section 13 Serial Communication Interface (SCI) Software standby Normal operation [1] [2] [3] [4] [5] Normal operation [1] [2] Figure 13.32 Clock Stop and Restart Procedure 13.8 Interrupt Sources 13.8.1 Interrupts in Normal Serial Communication Interface Mode Table 13.12 shows the interrupt sources in normal serial communication interface mode.
Section 13 Serial Communication Interface (SCI) Table 13.12 SCI Interrupt Sources Channel Name 1 3 13.8.
Section 13 Serial Communication Interface (SCI) error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DTC, be sure to set and enable the DTC prior to making SCI settings. For DTC settings, see section 7, Data Transfer Controller (DTC).
Section 13 Serial Communication Interface (SCI) 13.9.4 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, FER, or RER) in SSR is set to 1, even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit in SCR is cleared to 0. 13.9.
Section 13 Serial Communication Interface (SCI) 13.9.7 SCI Operations during Mode Transitions Transmission: Before making the transition to module stop or software standby, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode cancellation. If the transition is made during data transmission, the data being transmitted will be undefined.
Section 13 Serial Communication Interface (SCI) Transmission No All data transmitted? [1] [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing TDRE to 0 after mode cancellation; however, if the DTC has been initiated, the data remaining in DTC RAM will be transmitted when TE and TIE are set to 1. Yes Read TEND flag in SSR No TEND = 1 Yes TE = 0 [2] [2] Also clear TIE and TEIE to 0 when they are 1.
Section 13 Serial Communication Interface (SCI) Transmission start Transmission end Transition to Software standby software standby mode cancelled mode TE bit SCK output pin TxD output pin Port input/output Port input/output Marking output Port Last TxD bit retained SCI TxD output Port input/output Port High output* SCI TxD output Note: Initialized in software standby mode Figure 13.
Section 13 Serial Communication Interface (SCI) Figure 13.37 shows a sample flowchart for mode transition during reception. Reception Read RDRF flag in SSR RDRF = 1 No [1] [1] Data being received will be invalid. Yes Read receive data in RDR [2] Module stop mode is included. RE = 0 [2] Make transition to software standby mode etc. Cancel software standby mode etc. Change operating mode? No Yes Initialization RE = 1 Start reception Figure 13.
Section 13 Serial Communication Interface (SCI) 13.9.8 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 13.38. Low pulse of half a cycle SCK/Port 1. Transmission end Data Bit 6 4. Low pulse output Bit 7 2. TE = 0 TE 3. C/A = 0 C/A CKE1 CKE0 Figure 13.
Section 13 Serial Communication Interface (SCI) High output SCK/Port 1. Transmission end Data Bit 6 Bit 7 TE 2. TE = 0 4. C/A = 0 C/A 3. CKE1 = 1 CKE1 5. CKE1 = 0 CKE0 Figure 13.39 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins Rev. 3.00 Sep.
Section 14 CRC Operation Circuit (CRC) Section 14 CRC Operation Circuit (CRC) This LSI has a cyclic redundancy check (CRC) operation circuit to enhance the reliability of data transfer in high-speed communications, etc. The CRC operation circuit detects errors in data blocks. 14.1 Features The features of the CRC operation circuit are listed below.
Section 14 CRC Operation Circuit (CRC) 14.2 Register Descriptions The CRC operation circuit has the following registers. • CRC control register (CRCCR) • CRC data input register (CRCDIR) • CRC data output register (CRCDOR) 14.2.1 CRC Control Register (CRCCR) CRCCR initializes the CRC operation circuit, switches the operation mode, and selects the generating polynomial. Bit Bit Name Initial Value R/W Description 7 DORCLR 0 W CRCDOR Clear Setting this bit to 1 clears CRCDOR to H'0000.
Section 14 CRC Operation Circuit (CRC) 14.2.2 CRC Data Input Register (CRCDIR) CRCDIR is an 8-bit readable/writable register, to which the bytes to be CRC-operated are written. The result is obtained in CRCDOR. 14.2.3 CRC Data Output Register (CRCDOR) CRCDOR is a 16-bit readable/writable register that contains the result of CRC operation when the bytes to be CRC-operated are written to CRCDIR after CRCDOR is cleared.
Section 14 CRC Operation Circuit (CRC) 1. Write H'87 to CRCCR 2. Write H'F0 to CRCDIR 7 CRCCR 7 0 0 1 0 0 0 1 CRCDIR 1 1 CRCDOR clearing 0 7 0 1 1 1 1 0 0 0 0 CRC code generation 0 7 CRCDORH 0 0 0 0 0 0 0 0 CRCDORH 1 1 1 0 1 1 1 1 CRCDORL 0 0 0 0 0 0 0 0 CRCDORL 0 0 0 1 1 1 1 1 3. Read from CRCDOR CRC code = H'EF1F 4.
Section 14 CRC Operation Circuit (CRC) 1. Serial reception (LSB first) Data CRC code 7 1 1 1 1 0 1 1 F 0 7 1 1 0 7 0 0 8 2. Write H'83 to CRCCR 1 1 1 7 1 1 F 1 1 0 0 F 0 0 0 0 0 0 0 0 1 1 CRCDIR 1 0 1 1 1 CRCDOR clearing 0 0 CRC code generation 0 7 0 7 CRCDORH 0 0 0 0 0 0 0 0 CRCDORH 1 1 1 1 0 1 1 1 CRCDORL 0 0 0 0 0 0 0 0 CRCDORL 1 0 0 0 1 1 1 1 1 0 1 1 1 4. Write H'8F to CRCDIR 5.
Section 14 CRC Operation Circuit (CRC) 1. Serial reception (MSB first) Data CRC code 7 Input 1 1 1 1 0 0 0 F 0 7 0 1 0 2. Write H'87 to CRCCR 1 1 0 1 1 E 0 7 1 0 0 0 F 0 1 1 1 0 0 0 1 1 1 CRCDIR 1 0 1 1 1 CRCDOR clearing 0 0 0 0 CRC code generation 0 7 0 7 CRCDORH 0 0 0 0 0 0 0 0 CRCDORH 1 1 1 0 1 1 1 1 CRCDORL 0 0 0 0 0 0 0 0 CRCDORL 0 0 0 1 1 1 1 1 1 1 1 1 1 4. Write H'EF to CRCDIR 5.
Section 14 CRC Operation Circuit (CRC) 14.4 Note on CRC Operation Circuit Note that the sequence to transmit the CRC code differs between LSB-first transmission and MSB-first transmission. 1. CRC code generation After specifying the operation method, write data to CRCDIR in the sequence of (1) → (2) → (3) → (4). 7 0 (1) → (2) → (3) → (4) CRCDIR CRC code generation 0 7 CRCDORH (5) CRCDORL (6) 2.
Section 14 CRC Operation Circuit (CRC) Rev. 3.00 Sep.
Section 15 I2C Bus Interface (IIC) 2 Section 15 I C Bus Interface (IIC) 2 2 This LSI has four-channels of I C bus interface (IIC). The I C bus interface conforms to and 2 provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register 2 configuration that controls the I C bus differs partly from the Philips configuration, however. 15.
Section 15 I2C Bus Interface (IIC) ⎯ Pins⎯SCL0 to SCL3 and SDA0 to SDA3 ⎯ (normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected. 2 Figure 15.1 shows a block diagram of the I C bus interface. Figure 15.2 shows an example of I/O 2 pin connections to external circuits. Since I C bus interface I/O pins are different in structure from normal port pins, they have different specifications for permissible applied voltages.
Section 15 I2C Bus Interface (IIC) VCC VDD VCC SCL SCL SDA SDA SCL in SDA out (Master) SCL in This LSI SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) SCL in SCL SDA SDA in SCL SDA SCL out (Slave 2) 2 Figure 15.2 I C Bus Interface Connections (Example: This LSI as Master) Rev. 3.00 Sep.
Section 15 I2C Bus Interface (IIC) 15.2 Input/Output Pins 2 Table 15.1 summarizes the input/output pins used by the I C bus interface. Table 15.
Section 15 I2C Bus Interface (IIC) 15.3 Register Descriptions 2 The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed.
Section 15 I2C Bus Interface (IIC) If IIC is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is transferred automatically from ICDRS to ICDRR, following reception of one frame of data using ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from ICDRS to ICDRR. Always set IIC to receive mode before reading from ICDR.
Section 15 I2C Bus Interface (IIC) 15.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. In slave mode, transmit/receive operations by the DTC are possible when the received address matches the 2 second slave address.
Section 15 I2C Bus Interface (IIC) Table 15.
Section 15 I2C Bus Interface (IIC) 15.3.4 2 I C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W MSB-First/LSB-First Select 0: MSB-first 1: LSB-first 2 Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit 2 This bit is valid only in master mode with the I C bus format.
Section 15 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 2 BC2 All 0 R/W Bit Counter 1 BC1 0 BC0 These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than B'000, the setting should be made while the SCL line is low. The bit counter is initialized to B'000 when a start condition is detected.
Section 15 I2C Bus Interface (IIC) 15.3.5 2 I C Bus Transfer Rate Select Register (IICX3) IICX3 selects the IIC transfer rate clock and sets the transfer rate of IIC channel 3. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ ⎯ ⎯ Reserved These bits cannot be modified. The read values are undefined. 3 TCSS 0 R/W Transfer Rate Clock Source Select 2 This bit selects a clock rate to be applied to the I C bus transfer rate.
Section 15 I2C Bus Interface (IIC) 2 Table 15.3 I C bus Transfer Rate (1) • TCSS = 0 STCR/ ICMR IICX3 Bit 5 Bit 4 Bit 3 IICXn CKS2 CKS1 CKS0 Clock φ = 20 MHz φ = 25 MHz 0 0 0 0 φ/28 714.3* 892.9* 1 φ/40 500.0* 625.0* 0 φ/48 416.7* 520.8* 1 φ/64 312.5 390.6 0 φ/80 250.0 312.5 1 φ/100 200.0 250.0 0 φ/112 178.6 223.2 1 φ/128 156.3 195.3 0 φ/56 357.1 446.4* 1 φ/80 250.0 312.5 0 φ/96 208.3 260.4 1 φ/128 156.3 195.3 0 φ/160 125.0 156.
Section 15 I2C Bus Interface (IIC) 2 Table 15.3 I C bus Transfer Rate (2) • TCSS = 1 STCR/ ICMR IICX3 Bit 5 Bit 4 Bit 3 IICXn CKS2 CKS1 CKS0 Clock φ = 20 MHz φ = 25 MHz 0 0 0 0 φ/56 357.1 446.4* 1 φ/80 250.0 312.5 0 φ/96 208.3 260.4 1 φ/128 156.3 195.3 0 φ/160 125.0 156.3 1 φ/200 100.0 125.0 0 φ/224 89.3 111.6 1 φ/256 78.1 97.7 0 φ/112 178.6 223.2 1 φ/160 125.0 156.3 0 φ/190 104.2 130.2 1 φ/256 78.1 97.7 0 φ/320 62.5 78.1 1 φ/400 50.
Section 15 I2C Bus Interface (IIC) 15.3.6 2 I C Bus Control Register (ICCR) 2 ICCR controls the I C bus interface and performs interrupt flag confirmation. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I C Bus Interface Enable 2 2 2 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized. SAR and SARX can be accessed.
Section 15 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 5 MST 0 R/W [MST clearing conditions] 4 TRS 0 R/W (1) When 0 is written by software 2 (2) When lost in bus contention in I C bus format master mode [MST setting conditions] (1) When 1 is written by software (for MST clearing condition 1) (2) When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] (1) When 0 is written by software (except for TRS setting condition 3) (
Section 15 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 2 BBSY 0 R/W* Bus Busy 0 SCP 1 W Start Condition/Stop Condition Prohibit In master mode • Writing 0 in BBSY and 0 in SCP: A stop condition is issued • Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued In slave mode • Writing to the BBSY flag is disabled.
Section 15 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W 1 IRIC 0 Description 2 R/(W)* I C Bus Interface Interrupt Request Flag 2 Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR and the WAIT bit in ICMR. See section 15.4.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR.
Section 15 I2C Bus Interface (IIC) Bit 1 Bit Name IRIC Initial Value R/W 0 Description 1 R/(W)* At the end of data transfer in clock synchronous serial format (rise of the 8th transmit/receive clock) When a start condition is detected with serial format selected When a condition occurs in which the ICDRE or ICDRF flag is set to 1.
Section 15 I2C Bus Interface (IIC) When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. 2 When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set.
Section 15 I2C Bus Interface (IIC) Table 15.
Section 15 I2C Bus Interface (IIC) Table 15.
Section 15 I2C Bus Interface (IIC) MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State 0 0 1 0 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 ⎯ Reception end with ICDRF=1 0 0 1 0 0 ⎯ ⎯ 0↓ 0↓ 0↓ ⎯ 0↓ ⎯ ICDR read with the above state 0 0 1 0 0 1↑/0 *2 ⎯ 0 0 0 ⎯ 1↑ ⎯ Automatic data transfer from ICDRS to ICDRR with the above state 0 ⎯ 0↓ 1↑/0 *3 0/1↑ 3 * ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0↓ Stop condition detected [Legend] 0: 0-state retained 1: 1-state retained ⎯: Previous st
Section 15 I2C Bus Interface (IIC) 15.3.7 2 I C Bus Status Register (ICSR) ICSR consists of status flags. Refer to tables 15.4 and 15.5 as well. Bit Bit Name Initial Value R/W 7 ESTP 0 R/(W)* Error Stop Condition Detection Flag Description 2 This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer.
Section 15 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W 4 AASX 0 R/(W)* Second Slave Address Recognition Flag Description 2 In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX.
Section 15 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W 2 AAS 0 R/(W)* Slave Address Recognition Flag Description 2 In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
Section 15 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 0 ACKB 0 R/W Acknowledge Bit Stores acknowledge data.
Section 15 I2C Bus Interface (IIC) 15.3.8 2 I C Bus Extended Control Register (ICXR) 2 ICXR enables or disables the I C bus interface interrupt generation and continuous receive operation, and indicates the status of receive/transmit operations. Bit Bit Name Initial Value R/W Description 7 STOPIM 0 R/W Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the stop condition is detected in slave mode.
Section 15 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 5 ICDRF 0 R Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out. [Setting conditions] • When data is received successfully and transferred from ICDRS to ICDRR.
Section 15 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 4 ICDRE 0 R Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has been complete, thus allowing the next data to be written to.
Section 15 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 3 ALIE 0 R/W Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt request when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost. 2 ALSL 0 R/W Arbitration Lost Condition Select Selects the condition under which arbitration is lost.
Section 15 I2C Bus Interface (IIC) 15.3.9 2 I C SMBus Control Register (ICSMBCR) ICSMBCR is used to support the System Management Bus (SMBus) specifications. To support the SMBus specification, SDA output data hold time should be specified in the range of 300 ns to 1000 ns. Table 15.6 shows the relationship between the ICSMBCR setting and output data hold time. When the SMBus is not supported, the initial value should not be changed. ICSMBCR is enabled to access when bit MSTP4 is cleared to 0.
Section 15 I2C Bus Interface (IIC) Table 15.6 Output Data Hold Time Output Data Hold Time (ns) SMBnE FSEL1 FSEL0 Min./Max. φ = 20 MHz φ = 25 MHz 0 ⎯ ⎯ Min. 100* 80* Max. 150* 120* Min. 150* 120* Max. 250* 200* Min. 200* 160* Max. 350 280* Min. 300 240* Max. 550 440 Min. 500 400 Max. 950 760 1 0 0 1 1 0 1 [Legend] Note: * n = 0 to 3 Since the value is outside the SMBus specification, it should not be set. Table 15.
Section 15 I2C Bus Interface (IIC) 15.4 Operation 15.4.1 I C Bus Data Format 2 2 2 The I C bus interface has an I C bus format and a serial format. 2 The I C bus formats are addressing formats with an acknowledge bit. These are shown in figures 15.3 (a) and (b). The first frame following a start condition always consists of 9 bits. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 15.4. 2 Figure 15.5 shows the I C bus timing.
Section 15 I2C Bus Interface (IIC) SDA SCL S 1–7 8 9 SLA R/W A 1–7 8 DATA 9 A 1–7 DATA 8 9 A/A P 2 Figure 15.5 I C Bus Timing 2 Table 15.8 I C Bus Data Format Symbols Symbol Description S Start condition. The master device drives SDA from high to low while SCL is high SLA Slave address. The master device selects the slave device.
Section 15 I2C Bus Interface (IIC) 15.4.2 Initialization Initialize the IIC by the procedure shown in figure 15.6 before starting transmission/reception of data.
Section 15 I2C Bus Interface (IIC) Figure 15.7 shows the sample flowchart for the operations in master transmit mode. Start Initialize IIC [1] Initialization Read BBSY in ICCR [2] Test the status of the SCL and SDA lines. No BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR [3] Select master transmit mode.
Section 15 I2C Bus Interface (IIC) The transmission procedure and operations by which data is sequentially transmitted in synchronization with ICDR (ICDRT) write operations, are described below. 1. Initialize the IIC as described in section 15.4.2, Initialization. 2. Read the BBSY flag in ICCR to confirm that the bus is free. 3. Set bits MST and TRS to 1 in ICCR to select master transmit mode. 4. Write 1 to BBSY and 0 to SCP in ICCR.
Section 15 I2C Bus Interface (IIC) Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is still data to be transmitted, go to step [9] to continue the next transmission operation. When the slave device has not acknowledged (ACKB bit is set to 1), operate step [12] to end transmission. 12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR.
Section 15 I2C Bus Interface (IIC) Stop condition issuance SCL (master output) 8 9 SDA Bit 0 (master output) Data 1 SDA (slave output) [7] 1 2 3 4 Bit 7 Bit 6 Bit 5 Bit 4 5 6 7 8 Bit 3 Bit 2 Bit 1 Bit 0 9 [10] Data 2 A A ICDRE IRIC IRTR ICDR Data 2 Data 1 User processing [9] ICDR write [9] IRIC clear [11] ACKB read [12] IRIC clear [12] BBSY set to 1 and SCP cleared to 0 (Stop condition issuance) Figure 15.
Section 15 I2C Bus Interface (IIC) Receive Operation Using the HNDS Function (HNDS = 1): Figure 15.10 shows the sample flowchart for the operations in master receive mode (HNDS = 1). Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR [1] Select receive mode. Set HNDS = 1 in ICXR Clear IRIC in ICCR Last receive? Yes [2] Start receiving. The first read is a dummy read.
Section 15 I2C Bus Interface (IIC) The reception procedure and operations by which the data reception process is provided in 1-byte units with SCL fixed low at each data reception are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Set the HNDS bit in ICXR to 1. Clear the IRIC flag to 0 to determine the end of reception.
Section 15 I2C Bus Interface (IIC) Master receive mode Master transmit mode SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read SCL (master output) 9 1 2 3 4 5 6 7 8 SDA (slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 2 Bit 7 Bit 6 9 [3] Data 1 SDA (master output) Data 2 A IRIC IRTR ICDRF ICDRR Data 1 Undefined value User processing [1] TRS cleared to 0 [5] ICDR read (Data 1) [4] IRIC clear [2] ICDR read (Dummy read) [1] IRIC
Section 15 I2C Bus Interface (IIC) Receive Operation Using the Wait Function: Figures 15.13 and 15.14 show the sample flowcharts for the operations in master receive mode (WAIT = 1). Master receive mode Set TRS = 0 in ICCR [1] Select receive mode. Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR Set WAIT = 1 in ICMR [2] Start receiving. The first read is a dummy read.
Section 15 I2C Bus Interface (IIC) Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR [1] Select receive mode. Clear IRIC in ICCR Set WAIT = 0 in ICMR Read ICDR [2] Start receiving. The first read is a dummy read. Read IRIC in ICCR No IRIC = 1? [3] Wait for a receive wait (Set IRIC at the fall of the 8 th clock) Yes No Set ACKB = 1 in ICSR [7] Set acknowledge data for the last reception.
Section 15 I2C Bus Interface (IIC) 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 to set the acknowledge data. Clear the HNDS bit in ICXR to 0 to cancel the handshake function. Clear the IRIC flag to 0, and then set the WAIT bit in ICMR to 1. 2. When ICDR is read (dummy data is read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. 3.
Section 15 I2C Bus Interface (IIC) (2) At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received. 13. Read the IRTR flag in ICSR. If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state. If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop condition. 14. If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state.
Section 15 I2C Bus Interface (IIC) [8] Wait for one clock pulse Stop condition generation SCL (master output) 8 9 SDA Bit 0 (slave output) Data 2 [3] SDA (master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 3 [3] A 9 [12] [12] A IRIC IRTR [4] IRTR=0 ICDR Data 1 User processing [13] IRTR=0 [4] IRTR=1 [13] IRTR=1 Data 2 [6] IRIC clear (to end wait insertion) [11] IRIC clear [10] ICDR read (Data 2) [9] Set TRS=1 [7] Set ACKB=1 Data 3 [15] W
Section 15 I2C Bus Interface (IIC) Receive Operation Using the HNDS Function (HNDS = 1): Figure 15.17 shows the sample flowchart for the operations in slave receive mode (HNDS = 1). Slave receive mode Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR and HNDS = 1 in ICXR Clear IRIC in ICCR ICDRF = 1? No [1] Initialization. Select slave receive mode. [2] Read the receive data remaining unread.
Section 15 I2C Bus Interface (IIC) The reception procedure and operations using the HNDS bit function by which data reception process is provided in 1-byte unit with SCL being fixed low at every data reception, are described below. 1. Initialize the IIC as described in section 15.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0.
Section 15 I2C Bus Interface (IIC) Start condition generation SCL (Pin waveform) SCL (master output) SCL (slave output) SDA (master output) SDA (slave output) [7] SCL is fixed low until ICDR is read 1 2 3 4 5 6 7 8 9 1 2 1 2 3 4 5 6 7 8 9 1 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Slave address Bit 7 R/W Bit 6 Data 1 [6] A Interrupt request occurrence IRIC ICDRF Address+R/W ICDRS ICDRR Address+R/W Undefined value User processing [2] ICDR read [8] IRIC
Section 15 I2C Bus Interface (IIC) Continuous Receive Operation: Figure 15.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0). Slave receive mode Set MST = 0 and TRS = 0 in ICCR [1] Select slave receive mode. Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR ICDRF = 1? No [2] Read the receive data remaining unread.
Section 15 I2C Bus Interface (IIC) The reception procedure and operations in slave receive are described below. 1. Initialize the IIC as described in section 15.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3.
Section 15 I2C Bus Interface (IIC) Receive operations can be performed continuously by repeating steps 9 to 13. 14. Confirm that the ICDRF flag is set to 1, and read ICDR. 15. Clear the IRIC flag.
Section 15 I2C Bus Interface (IIC) Stop condition detection SCL (master output) 8 9 SDA (master output) Bit 0 Data (n-2) SDA (slave output) 1 2 3 4 5 6 7 8 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [11] Data (n-1) A 1 2 3 4 5 6 7 8 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [11] Data (n) A [11] [12] A IRIC ICDRF ICDRS Data (n-2) ICDRR Data (n-1) Data (n-2) [9] Wait for one frame User processing [13] IRIC clear Data (n) Data (n-1) [13] IRIC clear [10] ICDR
Section 15 I2C Bus Interface (IIC) 15.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 15.23 shows the sample flowchart for the operations in slave transmit mode.
Section 15 I2C Bus Interface (IIC) In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Initialize slave receive mode and wait for slave address reception. 2.
Section 15 I2C Bus Interface (IIC) 9. Dummy-read ICDR to release SCL on the slave side. 10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to 0.
Section 15 I2C Bus Interface (IIC) 15.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figures 15.25 to 15.27 show the IRIC set timing and SCL control.
Section 15 I2C Bus Interface (IIC) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL SDA 8 9 1 2 3 8 A 1 2 3 IRIC User processing Clear IRIC Clear IRIC (a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception. SCL SDA 8 9 1 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception. Figure 15.
Section 15 I2C Bus Interface (IIC) When FS = 1 and FSX = 1 (clocked synchronous serial format) SCL SDA 7 8 7 8 1 1 2 2 3 3 4 4 IRIC User processing Clear IRIC (a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception. SCL SDA 7 8 1 7 8 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) (b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception. Figure 15.27 IRIC Setting Timing and SCL Control (3) Rev. 3.
Section 15 I2C Bus Interface (IIC) 15.4.8 Operation Using the DTC This LSI provides the DTC to allow continuous data transfer. The DTC is initiated when the IRTR flag is set to 1, which is one of the two interrupt flags (IRTR and IRIC). When the ACKE bit is 0, the ICDRE, IRIC, and IRTR flags are set at the end of data transmission regardless of the acknowledge bit value.
Section 15 I2C Bus Interface (IIC) Table 15.
Section 15 I2C Bus Interface (IIC) 15.4.9 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 15.28 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
Section 15 I2C Bus Interface (IIC) The following items are not initialized: • Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR(other than ICDRE and ICDRF)) • Internal latches used to retain register read information for setting/clearing flags in the ICMR, ICCR, and ICSR registers • The value of the ICMR register bit counter (BC2 to BC0) • Generated interrupt sources (interrupt sources transferred to the interrupt controller) Notes on Initialization: • Interrupt flags and interrupt sources ar
Section 15 I2C Bus Interface (IIC) 15.5 Interrupt Source The IIC interrupt source is IICI. The IIC interrupt sources and their priority order are shown in table 15.10. Each interrupt source is enabled or disabled by the ICCR interrupt enable bit and transferred to the interrupt controller independently. Table 15.
Section 15 I2C Bus Interface (IIC) 15.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions*, after issuing the instruction that generates the start 2 condition, read the relevant DR registers of I C bus output pins, check that SCL and SDA are both low.
Section 15 I2C Bus Interface (IIC) 4. SCL and SDA input are sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in section 24, Electrical 2 Characteristics. Note that the I C bus interface AC timing specification will not be met with a system clock frequency of less than 5 MHz. 2 5. The I C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for high2 speed mode).
Section 15 I2C Bus Interface (IIC) 2 tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices 2 whose input timing permits this output timing for use as slave devices connected to the I C bus.
Section 15 I2C Bus Interface (IIC) 2 Table 15.13 I C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] 2 I C Bus tcyc tSr/tSf Influence Specification Item Indication (Max.) (Min.) φ = 20 MHz φ = 25 MHz ⎯ ⎯ Standard mode ⎯ ⎯ φ/200 φ/224 ⎯ ⎯ High-speed mode ⎯ ⎯ φ/48 φ/56 tSCLHO 0.5 tSCLO (–tSr) Standard mode –1000 4000 4000 3480 High-speed mode 300 600 900 820 tSCLLO tBUFO tSTAHO tSTASO tSTOSO 0.
Section 15 I2C Bus Interface (IIC) 3. 2 Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.). 7. Notes on ICDR register read at end of master reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
Section 15 I2C Bus Interface (IIC) Stop condition Start condition (a) SDA Bit 0 A SCL 8 9 Internal clock BBSY bit Master receive mode ICDR read disabled period Execution of instruction for issuing stop condition (write 0 to BBSY and SCP) Confirmation of stop condition issuance (read BBSY = 0) Start condition issuance Figure 15.29 Notes on Reading Master Receive Data Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in ICXR. 8.
Section 15 I2C Bus Interface (IIC) No IRIC = 1? [1] Wait for end of 1-byte transfer [1] Yes [2] Determine whether SCL is low Clear IRIC in ICCR [3] Issue start condition instruction for retransmission Read SCL pin No SCL = Low? [4] Determine whether start condition is generated or not [2] Yes [5] Set transmit data (slave address + R/W) Set BBSY = 1, SCP = 0 (ICCR) [3] No IRIC = 1? [4] Note: Program so that processing from [3] to [5] is executed continuously.
Section 15 I2C Bus Interface (IIC) 2 9. Note on when I C bus interface stop condition instruction is issued In a situation where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low.
Section 15 I2C Bus Interface (IIC) Secures a high period SCL VIH SCL = low detected SDA IRIC [1] SCL = low determination [2] IRIC clear Figure 15.32 IRIC Flag Clearing Timing When WAIT = 1 Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 11. Note on ICDR register read and ICCR register access in slave transmit mode 2 In I C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR during the time shaded in figure 15.33.
Section 15 I2C Bus Interface (IIC) Waveform at problem occurrence SDA R/W A SCL 8 9 TRS bit Bit 7 Address reception Data transmission ICDR read and ICCR read/write are disabled ICDR write (6 system clock period) The rise of the 9th clock is detected Figure 15.33 ICDR Register Read and ICCR Register Access Timing in Slave Transmit Mode Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 12.
Section 15 I2C Bus Interface (IIC) Restart condition (a) (b) A SDA SCL TRS 8 9 1 Data transmission 2 3 4 5 6 7 8 9 Address reception TRS bit setting is suspended in this period ICDR dummy read TRS bit setting The rise of the 9th clock is detected The rise of the 9th clock is detected Figure 15.34 TRS Bit Set Timing in Slave Mode Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in ICXR. 13.
Section 15 I2C Bus Interface (IIC) 14. Note on ACKE and TRS bits in slave mode 2 In the I C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit mode (TRS = 1) and then the address is received in slave mode without performing appropriate processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the address does not match.
Section 15 I2C Bus Interface (IIC) • Arbitration is lost • The AL flag in ICSR is set to 1 I2C bus interface (Master transmit mode) S SLA R/W A DATA1 Transmit data match Transmit timing match Other device (Master transmit mode) S SLA R/W A Transmit data does not match DATA2 A DATA3 A Data contention I2C bus interface (Slave receive mode) S SLA R/W A • Receive address is ignored SLA R/W A DATA4 A • Automatically transferred to slave receive mode • Receive data is recognized as a
Section 16 LPC Interface (LPC) Section 16 LPC Interface (LPC) This LSI has an on-chip LPC interface. The LPC includes three register sets, each of which comprises data and status registers, control register, and the host interrupt request circuit. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock. It uses four signal lines for address/data and one for host interrupt requests. This LPC module supports I/O read and I/O write cycle transfers. 16.
Section 16 LPC Interface (LPC) Figure 16.1 shows a block diagram of the LPC.
Section 16 LPC Interface (LPC) 16.2 Input/Output Pins Table 16.1 lists the LPC pin configuration. Table 16.
Section 16 LPC Interface (LPC) 16.3 Register Descriptions The LPC has the following registers.
Section 16 LPC Interface (LPC) The following registers are necessary for SMIC mode • SMIC flag register (SMICFLG) • SMIC control/status register (SMICCSR) • SMIC data register (SMICDTR) • SMIC interrupt register 0 (SMICIR0) • SMIC interrupt register 1 (SMICIR1) The following registers are necessary for BT mode • BT status register 0 (BTSR0) • BT status register 1 (BTSR1) • BT control/status register 0 (BTCSR0) • BT control/status register 1 (BTCSR1) • BT control register (BTCR) • BT data buffer (BTDTR) • B
Section 16 LPC Interface (LPC) 16.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1) HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits that determine pin output and the internal state of the LPC interface, and status flags that monitor the internal state of the LPC interface.
Section 16 LPC Interface (LPC) R/W Bit Initial Bit Name Value Slave Host Description 4 ⎯ R/W 0 ⎯ Reserved The initial value should not be changed. 3 SDWNE 0 R/W ⎯ LPC Software Shutdown Enable Controls LPC interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 16.4.5, LPC Interface Shutdown Function.
Section 16 LPC Interface (LPC) • HICR1 Bit Bit Name Initial Value 7 LPCBSY 0 R/W Slave Host Description R ⎯ LPC Busy Indicates that the LPC interface is processing a transfer cycle.
Section 16 LPC Interface (LPC) R/W Bit Initial Bit Name Value Slave Host Description 6 CLKREQ 0 R ⎯ LCLK Request Indicates that the LPC interface's SERIRQ output is requesting a restart of LCLK.
Section 16 LPC Interface (LPC) R/W Bit Initial Bit Name Value Slave Host Description 4 LRSTB R/W 0 ⎯ LPC Software Reset Bit Resets the LPC interface. For the scope of initialization by an LPC reset, see section 16.4.5, LPC Interface Shutdown Function. 0: Normal state [Clearing conditions] • Writing 0 • LPC hardware reset 1: LPC software reset state [Setting condition] Writing 1 after reading LRSTB = 0 3 SDWNB 0 R/W ⎯ LPC Software Shutdown Bit Controls LPC interface shutdown.
Section 16 LPC Interface (LPC) 16.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3) HICR2 controls interrupts to an LPC interface slave (this LSI). HICR3 monitors the states of the LPC interface pins. Bits 6 to 0 in HICR2 are initialized to H'00 by a reset. The states of other bits are decided by the pin states. The pin states can be monitored by the pin monitoring bits regardless of the LPC interface operating state or the operating state of the functions that use pin multiplexing.
Section 16 LPC Interface (LPC) Bit Bit Name Initial Value 3 IBFIE3 0 R/W Slave Host Description R/W ⎯ IDR3 and TWR Receive Complete interrupt Enable Enables or disables IBFI3 interrupt to the slave (this LSI).
Section 16 LPC Interface (LPC) Bit Bit Name Initial Value 0 ERRIE 0 R/W Slave Host Description R/W ⎯ Error Interrupt Enable Enables or disables ERRI interrupt to the slave (this LSI). 0: Error interrupt requests disabled 1: Error interrupt requests enabled Note: * Only 0 can be written to bits 6 to 4, to clear the flag.
Section 16 LPC Interface (LPC) 16.3.3 Host Interface Control Register 4 (HICR4) HICR4 controls the operation of the KCS, SMIC, and BT interface functions on channel 3. R/W Bit Bit Name Initial Value Slave Host Description 7 LADR12SEL 0 R/W ⎯ Switches the channel accessed via LADR12H and LADR12L. 0: LADR1 is selected 1: LADR2 is selected 6 ⎯ 0 R/W ⎯ Reserved The initial value should not be changed. 5 CH2OFFSEL 0 R/W ⎯ Channel 2 Offset Selects the address offset for LPC channel 2.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 1 SMICENBL 0 R/W ⎯ Enables or disables the use of the SMIC interface included in channel 3. When the LPC3E bit in HICR0 is 0, this bit is valid. 0: SMIC interface operation is disabled No address (LADR3) matches for SMICFLG, SSMICCSR, or SMICDTR 1: SMIC interface operation is enabled 0 BTENBL 0 R/W ⎯ Enables or disables the use of the BT interface included in channel 3.
Section 16 LPC Interface (LPC) Table 16.2 LADR1, LADR2 Initial Values Register Name Initial Value Description LADR1 H'0060 I/O address of channel 1 LADR2 H'0062 I/O address of channel 2 Table 16.
Section 16 LPC Interface (LPC) 16.3.5 LPC Channel 3 Address Register H, L (LADR3H, LADR3L) LADR3 comprises two 8-bit readable/writable registers that perform LPC channel 3 host address setting and control the operation of the bidirectional data registers. The contents of the address field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
Section 16 LPC Interface (LPC) When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4 of LADR3 is inverted, and the values of bits 3 to 0 are ignored.
Section 16 LPC Interface (LPC) • KCS mode I/O Address Bits 15 to5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection Bits 15 to5 Bit 4 0 0 1 0 I/O write IDR3 write, C/D3 ← 0 Bits 15 to5 Bit 4 0 0 1 1 I/O write IDR3 write, C/D3 ← 1 Bits 15 to5 Bit 4 0 0 1 0 I/O read ODR3 read Bits 15 to5 Bit 4 0 0 1 1 I/O read STR3 read • BT mode I/O Address Bits 15 to5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection Bits 15 to5 Bit 4 0
Section 16 LPC Interface (LPC) 16.3.6 Input Data Registers 1 to 3 (IDR1 to IDR3) The IDR registers are 8-bit read-only registers to the slave processor (this LSI), and 8-bit writeonly registers to the host processor. The registers selected from the host according to the I/O address are described in the following sections: for information on IDR1 and IDR2 selection, see section 16.3.4, LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L), and for information on IDR3 selection, see section 16.3.
Section 16 LPC Interface (LPC) 16.3.8 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave processor (this LSI) and the host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the same address for both the host address and the slave address.
Section 16 LPC Interface (LPC) 16.3.9 Status Registers 1 to 3 (STR1 to STR3) The STR registers are 8-bit registers that indicate status information during LPC interface processing. Bits 3, 1, and 0 in STR1 to STR3 are read-only bits to both the host processor and the slave processor (this LSI). However, 0 only can be written from the slave processor (this LSI) to bit 0 in STR1 to STR3, and bits 6 and 4 in STR3, in order to clear the flags to 0.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 1 IBF1 0 R R Input Data Register Full Indicates whether or not there is receive data in IDR1. This bit is an internal interrupt source to the slave processor (this LSI).
Section 16 LPC Interface (LPC) • STR2 R/W Bit Bit Name Initial Value Slave Host Description 7 DBU27 0 R/W R Defined by User 6 DBU26 0 R/W R The user can use these bits as necessary. 5 DBU25 0 R/W R 4 DBU24 0 R/W R 3 C/D2 0 R R Command/Data When the host writes to IDR2, bit 2 of the I/O address (when CH2OFFSEL1 = 0) or bit 0 of the I/O address (when CH2OFFSEL1 = 1) is written to this bit to indicate whether IDR2 contains data or a command.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 0 OBF2 0 R/(W)* R Output Data Register Full Indicates whether or not there is transmit data in ODR2. 0: There is not transmit data in ODR2 [Clearing conditions] • When the host reads ODR2 in an I/O read cycle • When the slave writes 0 to bit OBF2 1: There is transmit data in ODR2 [Setting condition] • Note: * When the slave writes to ODR2 Only 0 can be written to clear the flag. Rev. 3.00 Sep.
Section 16 LPC Interface (LPC) • STR3 (TWRE = 1 or SELSTR3 = 0) R/W Bit Bit Name Initial Value Slave Host Description 7 IBF3B 0 R R Bidirectional Data Register Input Buffer Full Flag This is an internal interrupt source to the slave (this LSI).
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 3 C/D3 R 0 R Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command. 0: Content of input data register (IDR3) is a data. 1: Content of input data register (IDR3) is a command. 2 DBU32 0 R/W R Defined by User The user can use this bit as necessary.
Section 16 LPC Interface (LPC) • STR3 (TWRE = 0 and SELSTR3 = 1) R/W Bit Bit Name Initial Value Slave Host Description 7 DBU37 0 R/W R Defined by User 6 DBU36 0 R/W R The user can use these bits as necessary. 5 DBU35 0 R/W R 4 DBU34 0 R/W R 3 C/D3 0 R R Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command. 0: Content of input data register (IDR3) is a data.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 0 OBF3A 0 R/(W)* R Output Data Register Full Indicates whether or not there is transmit data in ODR3. 0: There is not receive data in ODR3. [Clearing conditions] • When the host reads ODR3 in an I/O read cycle • When the slave writes 0 to bit OBF3A 1: There is receive data in ODR3. [Setting condition] • When the slave writes to ODR3 Note: * Only 0 can be written to clear the flag. Rev. 3.00 Sep.
Section 16 LPC Interface (LPC) 16.3.10 SERIRQ Control Register 0 (SIRQCR0) SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. R/W Bit Bit Name Initial Value Slave Host Description 7 Q/C 0 R ⎯ Quiet/Continuous Mode Flag Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame).
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 4 SMIE3B 0 R/W ⎯ Host SMI Interrupt Enable 3B Enables or disables an SMI interrupt request when OBF3B is set by a TWR15 write. 0: Host SMI interrupt request by OBF3B and SMIE3B is disabled [Clearing conditions] • Writing 0 to SMIE3B • LPC hardware reset, LPC software reset • Clearing OBF3B to 0 (when IEDIR3 = 0) 1: [When IEDIR3 = 0] Host SMI interrupt request by setting OBF3B to 1 is enabled.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 2 SMIE2 0 R/W ⎯ Host SMI Interrupt Enable 2 Enables or disables an SMI interrupt request when OBF2 is set by an ODR2 write. 0: Host SMI interrupt request by OBF2 and SMIE2 is disabled [Clearing conditions] • Writing 0 to SMIE2 • LPC hardware reset, LPC software reset • Clearing OBF2 to 0 (when IEDIR2 = 0) 1: [When IEDIR2 = 0] Host SMI interrupt request by setting OBF2 to 1 is enabled.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 0 IRQ1E1 0 R/W ⎯ Host IRQ1 Interrupt Enable 1 Enables or disables a host HIRQ1 interrupt request when OBF1 is set by an ODR1 write.
Section 16 LPC Interface (LPC) 16.3.11 SERIRQ Control Register 1 (SIRQCR1) SIRQCR1 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. R/W Bit Bit Name Initial Value Slave Host Description 7 IRQ11E3 0 R/W ⎯ Host IRQ11 Interrupt Enable 3 Enables or disables an HIRQ11 interrupt request when OBF3A is set by an ODR3 write.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 5 IRQ9E3 0 R/W ⎯ Host IRQ9 Interrupt Enable 3 Enables or disables an HIRQ9 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ9 interrupt request by OBF3A and IRQE9E3 is disabled. [Clearing conditions] • Writing 0 to IRQ9E3 • LPC hardware reset, LPC software reset • Clearing OBF3A to 0 (when IEDIR3 = 0) 1: [When IEDIR3 = 0] HIRQ9 interrupt request by setting OBF3A to 1 is enabled.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 3 IRQ11E2 0 R/W ⎯ Host IRQ11 Interrupt Enable 2 Enables or disables an HIRQ11 interrupt request when OBF2 is set by an oDR2 write. 0: HIRQ11 interrupt request by OBF2 and IRQE11E2 is disabled. [Clearing conditions] • Writing 0 to IRQ11E2 • LPC hardware reset, LPC software reset • Clearing OBF2 to 0 (when IEDIR2 = 0) 1: [When IEDIR2 = 0] HIRQ11 interrupt request by setting OBF2 to 1 is enabled.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 1 IRQ9E2 0 R/W ⎯ Host IRQ9 Interrupt Enable 2 Enables or disables an HIRQ9 interrupt request when OBF2 is set by an oDR2 write. 0: HIRQ9 interrupt request by OBF2 and IRQE9E2 is disabled. [Clearing conditions] • Writing 0 to IRQ9E2 • LPC hardware reset, LPC software reset • Clearing OBF2 to 0 (when IEDIR2 = 0) 1: [When IEDIR2 = 0] HIRQ9 interrupt request by setting OBF2 to 1 is enabled.
Section 16 LPC Interface (LPC) 16.3.12 SERIRQ Control Register 2 (SIRQCR2) SIRQCR2 contains bits that enable or disable SERIRQ interrupt requests and select the host interrupt request outputs. R/W Bit Bit Name Initial Value Slave Host Description 7 IEDIR3 0 R/W ⎯ Interrupt Enable Direct Mode 3 Selects whether an SERIRQ interrupt generation of LPC channel 3 is affected only by a host interrupt enable bit or by an OBF flag in addition to the enable bit.
Section 16 LPC Interface (LPC) 16.3.13 SERIRQ Control Register 4 (SIRQCR4) SIRQCR4 controls LPC interrupt requests to the host.
Section 16 LPC Interface (LPC) 16.3.14 SERIRQ Control Register 5 (SIRQCR5) SIRQCR5 selects the output of the host interrupt request signal of each frame. R/W Bit Bit Name Initial Value 7 SELIRQ15 0 R/W ⎯ SERIRQ Output Select 6 SELIRQ14 0 R/W ⎯ 5 SELIRQ13 0 R/W ⎯ 4 SELIRQ8 0 R/W ⎯ These bits select the state of the output on the pin for LPC host interrupt requests (HIRQ15, HIRQ14, HIRQ13, HIRQ8, HIRQ7, HIRQ5, HIRQ4, and HIRQ3).
Section 16 LPC Interface (LPC) 16.3.15 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt request signal of each frame. Bit Bit Name Initial Value 7 SELSTR3 0 R/W Slave Host Description R/W ⎯ Status Register 3 Selection Selects the function of bits 7 to 4 in STR3 in combination with the TWRE bit in LADR3L. For details of STR3, see section 16.3.9, Status Registers 1 to 3 (STR1 to STR3).
Section 16 LPC Interface (LPC) 16.3.16 SMIC Flag Register (SMICFLG) SMICFLG is one of the registers used to implement SMIC mode. This register includes bits that indicate whether or not the system is ready to data transfer and those that are used for handshake of the transfer cycles. R/W Bit Bit Name Initial Value Slave Host Description 7 0 RX_DATA_RDY R/W R Read Transfer Ready Indicates whether or not the slave is ready for the host read transfer. 0: Slave waits for ready status.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 1 ⎯ 0 R/W R Reserved The initial value should not be changed. 0 BUSY 0 R/(W)* W SMIC Busy This bit indicates that the slave is now transferring data. This bit can be cleared only by the slave and set only by the host. The rising edge of this bit is a source of internal interrupt to the slave. 0: Transfer cycle wait state [Clearing conditions] After the slave reads BUSY = 1, writes 0 to this bit.
Section 16 LPC Interface (LPC) 16.3.19 SMIC Interrupt Register 0 (SMICIR0) SMICIR0 is one of the registers used to implement SMIC mode. This register includes the bits that indicate the source of interrupt to the slave. R/W Bit Bit Name Initial Value Slave Host Description 7 to 5 ⎯ All 0 R/W ⎯ Reserved The initial value should not be changed.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 2 STARI 0 R/(W)* ⎯ Status Code Receive End Interrupt This is a status flag that indicates that the host has finished receiving the status code from SMICCSR. When the IBFIE3 bit and STARIE bit are set to 1, the IBFI3 interrupt is requested to the slave. 0: Status code receive wait state [Clearing condition] After the slave reads STARI = 1, writes 0 to this bit.
Section 16 LPC Interface (LPC) 16.3.20 SMIC Interrupt Register 1 (SMICIR1) SMICIR1 is one of the registers used to implement SMIC mode. This register includes the bits that enables/disables an interrupt to the slave. The IBFI3 interrupt is enabled by setting the IBFIE3 bit in HICR2 to 1. R/W Bit Bit Name Initial Value Slave Host Description 7 to 5 ⎯ 4 All 0 HDTWIE 0 R/W ⎯ Reserved The initial value should not be changed.
Section 16 LPC Interface (LPC) 16.3.21 BT Status Register 0 (BTSR0) BTSR0 is one of the registers used to implement BT mode. This register includes flags that control interrupts to the slave (this LSI). R/W Bit Bit Name Initial Value Slave Host Description 7 to 5 ⎯ All 0 R/W ⎯ Reserved The initial value should not be changed. 4 FRDI 0 R/(W)* ⎯ FIFO Read Request Interrupt This status flag indicates that host writes the data to BTDTR buffer with FIFO full state at the host write transfer.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 2 HWRI 0 R/(W)* ⎯ BT Host Write Interrupt This status flag indicates that the host writes 1byte to BTDTR buffer. When the IBFIE3 bit and HWRIE bit are set to 1, IBFI3 interrupt is requested to the slave. 0: Host BTDTR write wait state [Clearing condition] After the slave reads HWRI = 1, writes 0 to this bit. 1: The host writes to BTDTR [Setting condition] The host writes one byte to BTDTR.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 0 HBTRI 0 R/(W)* ⎯ BTDTR Host Read End Interrupt This status flag indicates that the host reads all valid data from BTDTR buffer. When the BFIE3 bit and HBTRIE bit are set to 1, IBFI3 interrupt is requested to the slave. 0: BTDTR host read end wait state [Clearing condition] After the slave reads HBTRI = 1 and writes 0 to this bit.
Section 16 LPC Interface (LPC) 16.3.22 BT Status Register 1 (BTSR1) BTSR1 is one of the registers used to implement the BT mode. This register includes a flag that controls an interrupt to the slave (this LSI). R/W Bit Bit Name Initial Value Slave Host Description 7 ⎯ 0 R/W ⎯ Reserved The initial value should not be changed. 6 HRSTI 0 R/(W)* ⎯ BT Reset Interrupt This status flag indicates that the BMC_HWRST bit in BTIMSR is set to 1 by the host.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 4 BEVTI 0 R/(W)* ⎯ BEVT_ATN Clear Interrupt This status flag indicates that the BEVT_ATN bit in BTCR is cleared by the host. When the IBFIE3 bit and BEVTIE bit are set to 1, IBFI3 interrupt is requested to the slave. 0: [Clearing condition] When the slave reads BEVTI = 1 and writes 0 to this bit. 1: [Setting condition] When the slave detects the falling edge of BEVT_ATN.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 1 CRRPI 0 R/(W)* ⎯ Read Pointer Clear Interrupt This status flag indicates that the CLR_RD_PTR bit in BTCR is set to 1 by the host. When the IBFIE3 bit and CRRPIE bit are set to 1, the IBFI3 interrupt is requested to the slave. 0: [Clearing condition] After the slave reads CRRPI = 1, writes 0 to this bit. 1: [Setting condition] When the slave detects the rising edge of CLR_RD_PTR.
Section 16 LPC Interface (LPC) 16.3.23 BT Control Status Register 0 (BTCSR0) BTCSR0 is one of the registers used to implement the BT mode. The BTCSR0 register contains the bits used to switch FIFOs in BT transfer, and enable or disable the interrupts to the slave (this LSI). The IBFI3 interrupt is enabled by setting the IBFIE3 bit in HICR2 to 1. R/W Bit Bit Name Initial Value Slave Host Description 7 ⎯ 0 R/W ⎯ Reserved The initial value should not be changed.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 1 HBTWIE 0 R/W ⎯ BTDTR Host Write Start Interrupt Enable Enables or disables the HBTWI interrupt which is an IBFI3 interrupt source to the slave. 0: BTDTR host write start interrupt is disabled. 1: BTDTR host write start interrupt is enabled. 0 HBTRIE 0 R/W ⎯ BTDTR Host Read End Interrupt Enable Enables or disables the HBTRI interrupt which is an IBFI3 interrupt source to the slave.
Section 16 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 5 0 IRQCRIE R/W ⎯ B2H_IRQ Clear Interrupt Enable Enables or disables the IRQCRI interrupt which is an IBFI3 interrupt source to the slave. 0: B2H_IRQ clear interrupt is disabled. 1: B2H_IRQ clear interrupt is enabled. 4 BEVTIE 0 R/W ⎯ BEVT_ATN Clear Interrupt Enable Enables or disables the BEVTI interrupt which is an IBFI3 interrupt source to the slave. 0: BEVT_ATN clear interrupt is disabled.
Section 16 LPC Interface (LPC) 16.3.25 BT Control Register (BTCR) BTCR is one of the registers used to implement BT mode. The BTCR register contains bits used in transfer cycle handshaking, and those indicating the completion of data transfer to the buffer. R/W Bit Bit Name Initial Value Slave Host 7 1 B_BUSY R/W Description R BT Write Transfer Busy Flag Read-only bit from the host. Indicates that the BTDTR buffer is being used for BT write transfer (write transfer is in progress.
Section 16 LPC Interface (LPC) R/W Bit Bit Name 4 Initial Value Slave BEVT_ATN 0 Host 1 Description 5 R/(W)* R/(W)* Event Interrupt Sets when the slave detects an event to the host. Setting the B2H_IRQ_EN bit in the BTIMSR register enables the BEVT_ATN bit to be used as an interrupt source to the host. 0: No event interrupt request is available [Clearing condition] When the host writes a 1 to the bit.
Section 16 LPC Interface (LPC) R/W Bit Bit Name 1 Initial Value CLR_RD_ 0 PTR Slave Host Description 2 R/(W)* (W)* 1 Read Pointer Clear This bit is used by the host to clear the read pointer during read transfer. A host read operation always yields 0 on readout. 0: Read pointer clear wait [Clearing condition] When the slave writes a 0 after a 1 has been read from CLR_RD_PTR. 1: Read pointer clear [Setting condition] When the host writes a 1.
Section 16 LPC Interface (LPC) 16.3.26 BT Data Buffer (BTDTR) BTDTR is used to implement the BT mode. BTDTR consists of two FIFOs: the host write transfer FIFO and the host read transfer FIFO. Their capacities are 64 bytes each. When using BTDTR, enable FIFO by means of the bits FSEL0 and FSEL1.
Section 16 LPC Interface (LPC) R/W Bit Bit Name 4 3 2 Initial Value Slave 0 0 0 OEM3 OEM2 OEM1 Host Description 4 R/(W)* User Defined Bit 4 R/(W)* These bits are defined by the user and are valid 4 R/(W)* only when set to 1 by a 0 written from the host. R/W R/W R/W 0: [Clearing condition] When the slave writes a 0, after a 1 has been read from OEM. 1: [Setting condition] When the slave writes a 1, after a 0 has been read from OEM, or when the host writes a 0.
Section 16 LPC Interface (LPC) 16.3.28 BT FIFO Valid Size Register 0 (BTFVSR0) BTFVSR0 is one of the registers used to implement BT mode. BTFVSR0 indicates a valid data size in the FIFO for host write transfer. R/W Bit Bit Name Initial Value Slave Host Description 7 to 0 N7 to N0 All 0 R ⎯ These bits indicate the number of valid bytes in the FIFO (the number of bytes which the slave can read) for host write transfer.
Section 16 LPC Interface (LPC) 16.4 Operation 16.4.1 LPC interface Activation The LPC interface is activated by setting any one of bits LPC3E to LPC1E in HICR0 to 1. When the LPC interface is activated, the related I/O port pins (PE7 to PE0) function as dedicated LPC interface input/output pins. Use the following procedure to activate the LPC interface after a reset release. 1. Read the signal line status and confirm that the LPC module can be connected.
Section 16 LPC Interface (LPC) An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of the LPC transfer cycle has been requested. In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the following order, in synchronization with LCLK.
Section 16 LPC Interface (LPC) LCLK LFRAME LAD3 to LAD0 Start ADDR TAR Sync Data TAR Start Cycle type, direction, and size Number of clocks 1 1 4 2 1 2 2 1 Figure 16.2 Typical LFRAME Timing LCLK LFRAME LAD3 to LAD0 Start ADDR Cycle type, direction, and size TAR Sync Slave must stop driving Master will drive high Too many Syncs cause timeout Figure 16.3 Abort Mechanism 16.4.3 SMIC Mode Transfer Flow Figure 16.4 shows the write transfer flow and figure 16.
Section 16 LPC Interface (LPC) Slave Host Wait for BUSY = 0 Host confirms the BUSY bit in SMICFLG. The bit indicates slave (this LSI) is ready for receiving a new control code. When BUSY = 1, access from host is disabled. Bit that indicates slave is ready for write transfer. Issues when slave is ready for the next write transfer. Wait for TX_DATA_RDY = 1 Host confirms the TX_DATA_RDY bit in SMICFLG. The confirmation is unnecessary when Write Start control is issued.
Section 16 LPC Interface (LPC) Slave Host Wait for BUSY = 0 Bit that indicates slave is ready for read transfer. Issues when slave is ready for the next read transfer. Slave waits for the BUSY bit in SMICFLG is set. Waits for RX_DATA_RDY = 1 A Write control code Slave confirms that control code is written to SMICCSR by host. The CTLWI bit in SMICIR0 is set. Host confirms the BUSY bit in SMICFLG. The bit indicates slave (this LSI) is ready for receiving a new control code.
Section 16 LPC Interface (LPC) 16.4.4 BT Mode Transfer Flow Figure 16.6 shows the write transfer flow and figure 16.7 shows the read transfer flow in BT mode. Slave Host Slave waits for the H2B_ATN bit (interrupt from host) is set. Wait for B_BUSY = 0 Host confirms the B_BUSY bit in BTCR. Wait for H2B_ATN = 0 Host confirms the H2B_ATN bit in BTCR. Clear write pointer Confirms the CLR_WR_PTR bit. The CRWPI bit in BTSR1 is set to notify write pointer clearing as an interrupt to slave.
Section 16 LPC Interface (LPC) Slave Host Slave confirms the H_BUSY bit in BTCR. Slave writes data of 1 to n bytes to the BTDTR buffer. Slave sets the B2H_ATN bit in BTCR to indicate data write completion to the BTDTR buffer. Wait for H_BUSY = 0 Write BTDTR buffer B2H_ATN = 1 Generate host interrupt H_BUSY = 1 Clear read pointer Confirms the CLR_RD_PTR bit. The CRRPI bit in BTSR1 is set to notify read pointer clearing as an interrupt source to slave. Host sets the H_BUSY bit in BTCR.
Section 16 LPC Interface (LPC) 16.4.5 LPC Interface Shutdown Function The LPC software shutdown state is controlled by the SDWNB bit. The LPC interface enters the reset state by itself, and is no longer affected by external signals other than the LRESET and LPCPD signals. Placing the slave in sleep mode or software standby mode is effective in reducing current dissipation in the shutdown state. In the LPC shutdown state, the LPC's internal state and some register bits are initialized.
Section 16 LPC Interface (LPC) Table 16.
Section 16 LPC Interface (LPC) Figure 16.8 shows the timing of the LRESET signals. LCLK LAD3 to LAD0 LFRAME At least 30 μs At least 100 μs At least 60 μs LRESET Figure 16.8 Power-Down State Termination Timing Rev. 3.00 Sep.
Section 16 LPC Interface (LPC) 16.4.6 LPC Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt. The timing is shown in figure 16.9.
Section 16 LPC Interface (LPC) The serialized interrupt transfer cycle frame configuration is as follows. Two of the states comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The recover state must be driven by the host or slave that was driving the preceding state. Table 16.
Section 16 LPC Interface (LPC) There are two modes⎯continuous mode and quiet mode⎯for serialized interrupts. The mode initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer cycle that ended before that cycle. In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet mode, the slave with interrupt sources requiring a request can also initiate an interrupt transfer cycle, in addition to the host.
Section 16 LPC Interface (LPC) 16.5 Interrupt Sources 16.5.1 IBFI1, IBFI2, IBFI3, and ERRI The host has four interrupt requests for the slave (this LSI): IBF1, IBF2, IBF3, and ERRI. IBFI1, IBFI2, and IBFI3 are IDR receive complete interrupts for IDR1, IDR2, and IDR3 and TWR, respectively. IBFI3 is also used for SMIC mode and BT mode interrupt requests. The ERRI interrupt indicates the occurrence of a special state such as an LPC reset, LPC shutdown, or transfer cycle abort.
Section 16 LPC Interface (LPC) 16.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9, HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15 The LPC interface can request 15 kinds of host interrupt by means of SERIRQ. HIRQ1 and HIRQ12 are used on LPC channel 1, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can be requested from LPC channels 2 and 3. For the SCIF, any one of 15 types of interrupts can be selected.
Section 16 LPC Interface (LPC) Table 16.
Section 16 LPC Interface (LPC) Slave CPU Master CPU ODR1 write Write 1 to IRQ1E1 SERIRQ IRQ1 output Interrupt initiation SERIRQ IRQ1 source clear ODR1 read OBF1 = 0? No Yes No All bytes transferred? Hardware operation Yes Software operation Figure 16.10 HIRQ Flowchart (Example of Channel 1) Rev. 3.00 Sep.
Section 16 LPC Interface (LPC) 16.6 Usage Note 16.6.1 Data Conflict The LPC interface provides buffering of asynchronous data from the host and slave (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid data conflict. For example, if the host and slave both try to access IDR or ODR at the same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be used to allow access only to data for which writing has finished.
Section 16 LPC Interface (LPC) Table 16.
Section 17 A/D Converter Section 17 A/D Converter This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to eight analog input channels to be selected. A block diagram of the A/D converter is shown in figure 17.1. 17.1 Features • 10-bit resolution • Eight input channels • Conversion time: 6.
Section 17 A/D Converter Internal data bus AVref 10-bit D/A AVSS Successive approximations register AVCC AN0 AN4 AN5 Multiplexer AN3 A D D R A A D D R B A D D R C A D D R D A D D R E A D D R F A D D R G A D D R H A D C S R A D C R + AN1 AN2 Bus interface Module data bus AN6 Comparator Control circuit Sample-and-hold circuit AN7 ADI interrupt signal Conversion start trigger from TMR_0 ADTRG [Legend] ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data re
Section 17 A/D Converter 17.2 Input/Output Pins Table 17.1 summarizes the pins used by the A/D converter. Table 17.
Section 17 A/D Converter 17.3 Register Descriptions The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D data register E (ADDRE) • A/D data register F (ADDRF) • A/D data register G (ADDRG) • A/D data register H (ADDRH) • A/D control/status register (ADCSR) • A/D control register (ADCR) Rev. 3.00 Sep.
Section 17 A/D Converter 17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) The ADDR are eight 16-bit read-only registers, ADDRA to ADDRH, which store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 17.2. The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter is 16-bit width and can be read directly from the CPU.
Section 17 A/D Converter 17.3.2 A/D Control/Status Register (ADCSR) The ADCSR controls the operation of the A/D conversion. Bit Bit Name Initial Value R/W 7 ADF 0 R/(W)* A/D End Flag Description A status flag that indicates the end of A/D conversion. This flag indicates that the results of A/D conversion are stored in the A/D data registers.
Section 17 A/D Converter Bit Initial Bit Name Value R/W Description 3 ⎯ 0 R/W Reserved The initial value should not be changed. 2 CH2 1 CH1 0 CH0 All 0 R/W Channel Select 2 to 0 Select analog input channels together with the SCANE bit and the SCANS bit of ADCR.
Section 17 A/D Converter 17.3.3 A/D Control Register (ADCR) The ADCR sets the operation mode of A/D converter and the conversion time. Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0, Extended Trigger Select 6 TRGS0 0 R/W Enable starting of A/D conversion by a trigger signal. 0 EXTRGS 0 R/W These bits should be set while A/D conversion is stopped (ADSF = 0). 00 0: Disables starting by trigger signals. 10 0: Enables starting by a trigger from TMR_0.
Section 17 A/D Converter 17.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. The ADST bit can be set to 1 at the same time as the operating mode or analog input channel is changed. 17.4.
Section 17 A/D Converter Set* ADIE ADST A/D conversion starts Set* Set* Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion 1 Idle A/D conversion 2 Idle ADDRA Read the result of conversion Result of A/D conversion 1 ADDRB Read the result of conversion Result of A/D conversion 2 ADDRC ADDRD Note : * indicates execution of a software instruction. Figure 17.
Section 17 A/D Converter 4. The ADST bit is not automatically cleared to 0 and steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the idle state. After that, when the ADST bit is set to 1, the operation starts from the first channel again.
Section 17 A/D Converter 17.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 17.4 shows the A/D conversion timing. Table 17.3 indicates the A/D conversion time. As indicated in figure 17.4, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL).
Section 17 A/D Converter (1) Pφ Address (2) Write signal Input sampling timing ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay tSPL: Input sampling time tCONV: A/D conversion time Figure 17.4 A/D Conversion Timing Rev. 3.00 Sep.
Section 17 A/D Converter Table 17.3 A/D Conversion Characteristics (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 1 CKS0 = 0 Item Symbol Min. Typ. Max. Min. Typ. Max. A/D conversion start delay time tD (6) ⎯ (9) (10) ⎯ (17) Input sampling time tSPL ⎯ 30 ⎯ ⎯ 60 ⎯ A/D conversion time tCONV 77 ⎯ 80 153 ⎯ 160 Note: Values in the table indicate the number of states. Table 17.
Section 17 A/D Converter 17.4.4 Timing of External Trigger Input A/D conversion can also be started by an externally input trigger signal. Setting the TRGS1 and TRGS0 bits in ADCSR to B'11 selects the signal on the ADTRG pin as an external trigger. The ADST bit in ADCSR is set to 1 on the falling edge of ADTRG, initiating A/D conversion. Other operations are the same as those in the case where the ADST bit is set to 1 by software, regardless of whether the converter is in single mode or scan mode.
Section 17 A/D Converter 17.6 A/D Conversion Accuracy Definitions This LSI’s A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.6).
Section 17 A/D Converter Digital output Ideal A/D conversion characteristic H'3FF H'3FE H'3FD H'004 H'003 H'002 Quantization error H'001 H'000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 17.6 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 17.7 A/D Conversion Accuracy Definitions Rev. 3.00 Sep.
Section 17 A/D Converter 17.7 Usage Notes 17.7.1 Setting of Module Stop Mode Operation of the A/D converter can be enabled or disabled by setting the module stop control register. By default, the A/D converter is stopped. Registers of the A/D converter only become accessible when it is released from module stop mode. See section 22, Power-Down Modes, for details. 17.7.
Section 17 A/D Converter 17.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect the absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. 17.7.
Section 17 A/D Converter 17.7.6 Notes on Noise Countermeasures In order to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7), a protection circuit should be connected between AVcc and AVss as shown in figure 17.9. Also, the bypass capacitors connected to AVcc and the filter capacitors connected to AN0 to AN7 must be connected to AVss.
Section 17 A/D Converter Table 17.6 Standard of Analog Pins Item Min. Max. Unit Analog input capacitance ⎯ 20 pF Acceptable signal source impedance ⎯ 5 kΩ 10 kΩ To A/D converter AN0 to AN7 20 pF Note: Values are reference values. Figure 17.10 Analog Input Pin Equivalent Circuit 17.7.
Section 17 A/D Converter Rev. 3.00 Sep.
Section 18 RAM Section 18 RAM This LSI has 40 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR). Rev. 3.00 Sep.
Section 18 RAM Rev. 3.00 Sep.
Section 19 Flash Memory Section 19 Flash Memory The flash memory has the following features. Figure 19.1 shows a block diagram of the flash memory. 19.1 • Features Size 512 Kbytes (ROM address: H'000000 to H'07FFFF) • Programming/erasing interface by the download of on-chip program This LSI has a dedicated programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the argument parameter.
Section 19 Flash Memory Internal address bus Internal data bus (16 bits) FCCS Module bus FPCS Memory MAT unit FECS FKEY Control unit FMATS User MAT: 512 Kbytes User boot MAT: 16 Kbytes FTDAR Flash memory FWE pin Mode pin [Legend] FCCS: FPCS: FECS: FKEY: FMATS: FTDAR: Operating mode Flash code control status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register Note: To read from
Section 19 Flash Memory 19.1.1 Operating Mode When each mode pin and the FWE pin are set in the reset state and reset start is performed, this LSI enters each operating mode as shown in figure 19.2. • Flash memory can be read in user mode, but cannot be programmed or erased. • Flash memory can be read, programmed, or erased on the board only in boot mode, user program mode, and user boot mode. • Flash memory can be read, programmed, or erased by means of the PROM programmer in programmer mode.
Section 19 Flash Memory 19.1.2 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and programmer mode is shown in table 19.1. Table 19.
Section 19 Flash Memory 19.1.3 Flash Memory MAT Configuration This LSI's flash memory is configured by the 16-Kbyte user boot MAT and 256-Kbyte user MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between two MATs, the MAT must be switched by using FMATS. The user MAT or user boot MAT can be read in all modes. However, the user boot MAT can be programmed only in boot mode and programmer mode.
Section 19 Flash Memory EB0 H'000000 H'000001 H'000002 →Programming unit: 128 bytes→ H'00007F Erase unit: 4 kbytes EB1 Erase unit: 4 kbytes EB2 Erase unit: 4 kbytes EB3 H'000F80 H'000F81 H'000F82 – – – – – – – – – – – – – – H'000FFF H'001000 H'001001 H'001002 →Programming unit: 128 bytes→ H'00107F H'001F80 H'001F81 H'001F82 – – – – – – – – – – – – – – H'001FFF H'002000 H'002001 H'002002 →Programming unit: 128 bytes→ H'00207F H'002F80 H'002F81 H'002F82 – – – – – – – – – – –
Section 19 Flash Memory 19.1.5 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface register/parameter. The procedure program is made by the user in user program mode and user boot mode. An overview of the procedure is given as follows. For details, see section 19.4.2, User Program Mode. Start user procedure program for programming/erasing.
Section 19 Flash Memory 2. Download of on-chip program The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control status register (FCCS), which are programming/erasing interface registers. The flash memory is replaced to the embedded program storage area when downloading.
Section 19 Flash Memory 19.2 Input/Output Pins Table 19.2 shows the flash memory pin configuration. Table 19.2 Pin Configuration Pin Name Input/Output Function RES Input Reset FWE Input Flash memory programming/erasing enable pin MD2 Input Sets operating mode of this LSI MD1 Input Sets operating mode of this LSI TxD1 Output Serial transmit data output (used in boot mode) RxD1 Input Serial receive data input (used in boot mode) 19.
Section 19 Flash Memory There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters are allocated for each operating mode and MAT selection. The correspondence of operating modes and registers/parameters for use is shown in table 19.3. Table 19.
Section 19 Flash Memory 19.3.1 Programming/Erasing Interface Register The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in byte. These registers are initialized at a reset or in hardware standby mode. • Flash Code Control Status Register (FCCS) FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of on-chip program.
Section 19 Flash Memory Bit Initial Bit Name Value R/W Description 4 FLER R Flash Memory Error 0 Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state. When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to flash memory, the reset must be released after the reset period of 100 μs which is longer than normal. 0: Flash memory operates normally.
Section 19 Flash Memory Bit Initial Bit Name Value R/W Description 3 WEINTE R/W Program/Erase Enable 0 Modifies the space for the interrupt vector table, when interrupt vector data is not read successfully during programming/erasing flash memory or switching between a user MAT and a user boot MAT. When this bit is set to 1, interrupt vector data is read from address spaces H'FFE080 to H'FFE0FF (on-chip RAM space), instead of from address spaces H'000000 to H'00007F (up to vector number 31).
Section 19 Flash Memory Bit Initial Bit Name Value R/W Description 0 SCO (R)/W* Source Program Copy Operation 0 Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM specified by FTDAR. In order to set this bit to 1, H′A5 must be written to FKEY and this operation must be executed in the on-chip RAM.
Section 19 Flash Memory • Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit Initial Bit Name Value R/W 7 to 1 ⎯ R/W All 0 Description Reserved The initial value should not be changed. 0 PPVS 0 R/W Program Pulse Verify Selects the programming program. 0: On-chip programming program is not selected. [Clearing condition] When transfer is completed 1: On-chip programming program is selected.
Section 19 Flash Memory • Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download onchip program or executing the downloaded programming/erasing program, these processing cannot be executed if the key code is not written.
Section 19 Flash Memory • Flash MAT Select Register (FMATS) FMATS specifies whether user MAT or user boot MAT is selected. Bit Initial Bit Name Value R/W Description 7 MS7 0/1* R/W MAT Select 6 MS6 0 R/W 5 MS5 0/1* R/W 4 MS4 0 R/W These bits are in user-MAT selection state when the value other than H'AA is written and in user-boot-MAT selection state when H'AA is written.
Section 19 Flash Memory • Flash Transfer Destination Address Register (FTDAR) FTDAR is a register that specifies the address to download an on-chip program. This register must be specified before setting the SCO bit in FCCS to 1. Bit Initial Bit Name Value R/W Description 7 TDER R/W Transfer Destination Address Setting Error 0 This bit is set to 1 when the address specified by bits TDA6 to TDA0, which is the start address to download an on-chip program, is over the range.
Section 19 Flash Memory 19.3.2 Programming/Erasing Interface Parameter The programming/erasing interface parameter specifies the operating frequency, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (ER0 and ER1) or the on-chip RAM area. The initial value is undefined at a reset or in hardware standby mode.
Section 19 Flash Memory Table 19.
Section 19 Flash Memory (1) Download Control The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area to be downloaded is the 3-Kbyte area starting from the address specified by FTDAR. Download control is set by the program/erase interface registers, and the DPFR parameter indicates the return value. (a) Download pass/fail result parameter (DPFR: single byte of start address specified by FTDAR) This parameter indicates the return value of the download result.
Section 19 Flash Memory Bit Initial Bit Name Value 0 SF ⎯ R/W Description R/W Success/Fail Returns the result whether download is ended normally or not. The determination result whether program that is downloaded to the on-chip RAM is read back and then transferred to the on-chip RAM is returned. 0: Downloading on-chip program is ended normally (no error) 1: Downloading on-chip program is ended abnormally (error occurs) Rev. 3.00 Sep.
Section 19 Flash Memory (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set. The initial program is set as a parameter of the programming/erasing program which has downloaded these settings.
Section 19 Flash Memory (b) Flash pass/fail parameter (FPFR: general register R0L of CPU) This parameter indicates the return value of the initialization result. Bit Initial Bit Name Value R/W Description 7 to 2 ⎯ ⎯ Unused ⎯ Return 0 1 FQ ⎯ R/W Frequency Error Detect Returns the check result whether the specified operating frequency of the CPU is in the range of the supported operating frequency.
Section 19 Flash Memory (a) Flash multipurpose address area parameter (FMPAR: general register ER1 of CPU) This parameter stores the start address of the programming destination on the user MAT. When the address in the area other than flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in FPFR.
Section 19 Flash Memory Bit Initial Bit Name Value 6 MD ⎯ R/W Description R/W Programming Mode Related Setting Error Detect Returns the check result that a high level signal is input to the FWE pin and the error protection state is not entered. When the low level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The state can be confirmed with the FWE and FLER bits in FCCS. For conditions to enter the error protection state, see section 19.5.
Section 19 Flash Memory Bit Initial Bit Name Value 2 WD ⎯ R/W Description R/W Write Data Address Detect When the address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs. 0: Setting of write data address is normal 1: Setting of write data address is abnormal 1 WA ⎯ R/W Write Address Error Detect When the following items are specified as the start address of the programming destination, an error occurs.
Section 19 Flash Memory (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded. This is set to the FEBS parameter (general register ER0). One block is specified from the block number 0 to 15. For details on the erasing processing procedure, see section 19.4.2, User Program Mode. (a) Flash erase block select parameter (FEBS: general register ER0 of CPU) This parameter specifies the erase-block number.
Section 19 Flash Memory (b) Flash pass/fail parameter (FPFR: general register R0L of CPU) This parameter returns value of the erasing processing result. Bit Initial Bit Name Value R/W Description 7 ⎯ ⎯ ⎯ Unused 6 MD ⎯ R/W Return 0. Programming Mode Related Setting Error Detect Returns the check result that a high level signal is input to the FWE pin and the error protection state is not entered.
Section 19 Flash Memory Bit Initial Bit Name Value 3 EB ⎯ R/W Description R/W Erase Block Select Error Detect Returns the check result whether the specified eraseblock number is in the block range of the user MAT. 0: Setting of erase-block number is normal 1: Setting of erase-block number is abnormal ⎯ 2, 1 ⎯ ⎯ Unused Return 0. 0 SF ⎯ R/W Success/Fail Indicates whether the erasing processing is ended normally or not.
Section 19 Flash Memory 19.4.1 Boot Mode Boot mode executes programming/erasing user MAT and user boot MAT by means of the control command and program data transmitted from the host using the on-chip SCI. The tool for transmitting the control command and program data must be prepared in the host. The SCI communication mode is set to asynchronous mode. When reset start is executed after this LSI’s pin is set in boot mode, the boot program in the microcomputer is initiated.
Section 19 Flash Memory (1) SCI Interface Setting by Host When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit adjustment end sign (1 byte of H'00) to the host.
Section 19 Flash Memory (2) State Transition Diagram The overview of the state transition diagram after boot mode is initiated is shown in figure 19.8. 1. Bit rate adjustment After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host. 2. Waiting for inquiry set command For inquiries about user-MAT size and configuration, MAT start address, and support state, the required information is transmitted to the host. 3.
Section 19 Flash Memory (Bit rate adjustment) H'00.......H'00 reception H'00 transmission (adjustment completed) Boot mode initiation (reset by boot mode) Bit rate adjustment H'55 2. ption rece Inquiry command reception Wait for inquiry setting command Inquiry command response 3. 4. 1.
Section 19 Flash Memory 19.4.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 19.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset or hardware standby must not be executed. Doing so may damage or destroy flash memory.
Section 19 Flash Memory (1) On-chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and determination of the result, must be executed in the on-chip RAM. The on-chip program that is to be downloaded is all in the on-chip RAM. Note that area in the on-chip RAM must be controlled so that these parts do not overlap. Figure 19.10 shows the program area to be downloaded.
Section 19 Flash Memory (2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 19.11. 1. Disable interrupts and bus master operation other than CPU Set FKEY to H'A5 2. Set FKEY to H'5A 10. Set SCO to 1 and execute download 3. Set parameters to ER1 and ER0 (FMPAR and FMPDR) 11. Clear FKEY to 0 4. Programming JSR FTDAR setting + 16 12. 5.
Section 19 Flash Memory 128-byte programming is performed in one program processing. When more than 128-byte programming is performed, programming destination address/program data parameter is updated in 128-byte units and programming is repeated. When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. If the dummy data to be added is H'FF, the program processing period can be shortened. 1.
Section 19 Flash Memory ⎯ After the on-chip program storage area is returned to the user-MAT space, the user procedure program is returned. ⎯ In the download processing, the values of general registers of the CPU are held. ⎯ In the download processing, any interrupts are not accepted. However, interrupt requests are held. Therefore, when the user procedure program is returned, the interrupts occur.
Section 19 Flash Memory 7. Initialization When a programming program is downloaded, the initialization program is also downloaded to the on-chip RAM. There is an entry point of the initialization program in the area from the start address specified by FTDAR + 32 bytes of the on-chip RAM. The subroutine is called and initialization is executed by using the following steps. MOV.
Section 19 Flash Memory 11. The parameter which is required for programming is set. The start address of the programming destination of the user MAT (FMPAR) is set to general register ER1. The start address of the program data area (FMPDR) is set to general register ER0. ⎯ Example of the FMPAR setting FMPAR specifies the programming destination address.
Section 19 Flash Memory 15. After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after user MAT programming has finished, secure the reset period (period of RES = 0) of 100 μs which is longer than normal. (3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 19.12.
Section 19 Flash Memory For the downloaded on-chip program area, refer to the RAM map for programming/erasing in figure 19.10. A single divided block is erased by one erasing processing. For block divisions, refer to figure 19.4. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. 1. Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time.
Section 19 Flash Memory 5. Determine whether erasure of the necessary blocks has completed. If more than one block is to be erased, update the FEBS parameter and repeat steps 2 to 5. Blocks that have already been erased can be erased again. 6. After erasure completes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after user MAT erasure has completed, secure the reset period (period of RES = 0) of 100 μs which is longer than normal.
Section 19 Flash Memory • Be careful not to damage on-chip RAM with overlapped settings. In addition to the erasing program area and programming program area, areas for the user procedure programs, work area, and stack area are reserved in on-chip RAM. Do not make settings that will overwrite data in these areas. • Be sure to initialize both the erasing program and programming program.
Section 19 Flash Memory 19.4.3 User Boot Mode This LSI has user boot mode which is initiated with different mode pin settings than those in boot mode or user program mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode.
Section 19 Flash Memory Start programming procedure program 1 Select on-chip program to be downloaded and specify download destination by FTDAR Set FMATS to value other than H'AA to select user MAT MAT switchover Yes No Download error processing Set the FPEFEQ parameters Initialization JSR FTDAR setting + 32 FPFR = 0 ? Set parameter to ER0 and ER1 (FMPAR and FMPDR) Programming Clear FKEY to 0 User-MAT selection state Download Set FKEY to H'A5 Set SCO to 1 and execute download DPFR = 0 ? In
Section 19 Flash Memory read is undetermined. Perform MAT switching in accordance with the description in section 19.6, Switching between User MAT and User Boot MAT. Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 19.4.4, Procedure Program and Storable Area for Programming Data. Rev. 3.00 Sep.
Section 19 Flash Memory (3) User MAT Erasing in User Boot Mode For erasing the user MAT in user boot mode, additional processing made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after erasing completes. Figure 19.15 shows the procedure for erasing the user MAT in user boot mode.
Section 19 Flash Memory MAT switching is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is read is undetermined. Perform MAT switching in accordance with the description in section 19.6, Switching between User MAT and User Boot MAT.
Section 19 Flash Memory 19.4.4 Procedure Program and Storable Area for Programming Data In the descriptions in the previous section, the programming/erasing procedure programs and storable areas for program data are assumed to be in the on-chip RAM. However, the program and the data can be stored in and executed from other areas, such as part of flash memory which is not to be programmed or erased, or somewhere in the external address space. (1) Conditions that Apply to Programming/Erasing 1.
Section 19 Flash Memory should be transferred to the on-chip RAM to place the address that FMPDR indicates in an area other than the flash memory. In consideration of these conditions, there are three factors; operating mode, the bank structure of the user MAT, and operations. The areas in which the programming data can be stored for execution are shown in tables. Table 19.7 Executable MAT Initiated Mode Operation User Program Mode User Boot Mode* Programming Table 19.8 (1) Table 19.
Section 19 Flash Memory Table 19.
Section 19 Flash Memory Storable /Executable Area Item On-chip RAM User MAT Execution of Programming × Determination of Program Result × Operation for Program Error × Operation for FKEY Clear × Note: * Selected MAT User MAT Transferring the data to the on-chip RAM enables this area to be used. Rev. 3.00 Sep.
Section 19 Flash Memory Table 19.
Section 19 Flash Memory Storable /Executable Area Item On-chip RAM User MAT Operation for Erasure Error × Operation for FKEY Clear × Rev. 3.00 Sep.
Section 19 Flash Memory Table 19.
Section 19 Flash Memory Storable/Executable Area Item On-chip RAM User Boot MAT Operation for Settings of Program Parameter × Execution of Programming × Determination of Program Result × Operation for Program Error ×* Operation for FKEY Clear × Switching MATs by FMATS × Selected MAT User MAT User Boot MAT Embedded Program Storage Area 2 Notes: 1. Transferring the data to the on-chip RAM enables this area to be used. 2.
Section 19 Flash Memory Table 19.
Section 19 Flash Memory Storable/Executable Area On-chip RAM Item User Boot MAT Operation for Settings of Erasure Parameter × Execution of Erasure × Determination of Erasure Result × Operation for Erasure Error ×* Operation for FKEY Clear × Switching MATs by FMATS × Note: * Selected MAT User MAT User Boot MAT Embedded Program Storage Area Switching FMATS by a program in the on-chip RAM enables this area to be used. Rev. 3.00 Sep.
Section 19 Flash Memory 19.5 Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 19.5.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization are possible.
Section 19 Flash Memory Table 19.9 Hardware Protection Function to be Protected Item Description FWE pin protection • When a low level signal is input to the ⎯ FWE pin, the FWE bit in FCCS is cleared and the program/eraseprotected state is entered. Reset/standby protection • The program/erase interface registers are initialized in the reset state (including a reset by the WDT) and standby mode and the program/eraseprotected state is entered.
Section 19 Flash Memory 19.5.2 Software Protection Software protection is set up in any of two ways: by disabling the downloading of on-chip programs for programming and erasing and by means of a key code. Table 19.10 Software Protection Function to be Protected Item Description Protection by the SCO bit • The program/erase-protected state is entered by clearing the SCO bit in FCCS which disables the downloading of the programming/erasing programs.
Section 19 Flash Memory 4. When a bus master other than the CPU, such as the DTC, gets bus mastership during programming/erasing. Error protection is cancelled only by a reset or by hardware-standby mode. Note that the reset should be released after the reset period of 100 μs which is longer than normal. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error-protection state has been entered.
Section 19 Flash Memory 19.6 Switching between User MAT and User Boot MAT It is possible to alternate between the user MAT and user boot MAT. However, the following procedure is required because these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or programmer mode.) 1. MAT switching by FMATS should always be executed from the on-chip RAM. 2.
Section 19 Flash Memory 19.7 Programmer Mode Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the programming and erasing of programs and data. In the programmer mode, a general-purpose PROM programmer, which supports microcomputers 1 with 512-Kbyte flash memory as a device type* , can freely be used to write programs to the on2 chip ROM. Program/erase is possible on the user MAT and user boot MAT* .
Section 19 Flash Memory 19.8 Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the internal SCI. The serial communication interface specification is shown below. (1) Status The boot program has three states. 1. Bit-Rate-Adjustment State In this state, the boot program adjusts the bit rate to communicate with the host.
Section 19 Flash Memory Reset Bit-rate-adjustment state Inquiry/response wait Response Inquiry Operations for inquiry and selection Transition to programming/erasing Operations for response Operations for erasing user MATs and user boot MATs Programming/erasing wait Programming Erasing Operations for programming Operations for erasing Figure 19.18 Boot Program States Rev. 3.00 Sep.
Section 19 Flash Memory (2) Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 19.19.
Section 19 Flash Memory 4. Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry. 5. Memory read response This response consists of 4 bytes of data.
Section 19 Flash Memory • Size (4 bytes): 4-byte response to a memory read (4) Inquiry and Selection States The boot program returns information from the flash memory in response to the host’s inquiry commands and sets the device code, clock mode, and bit rate in response to the host’s selection command. Inquiry and selection commands are listed below. Table 19.
Section 19 Flash Memory The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. These commands will certainly be needed. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40).
Section 19 Flash Memory (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command • H'10 Size Device code SUM Command, H'10, (1 byte): Device selection • Size (1 byte): Amount of device-code data This is fixed at 4.
Section 19 Flash Memory (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command H'11 Size Mode SUM • Command, H'11, (1 byte): Selection of clock mode • Size (1 byte): Amount of data that represents the modes • Mode (1 byte): A clock mode returned in reply to the supported clock mode inquiry.
Section 19 Flash Memory (e) Multiplication Ratio Inquiry The boot program will return the supported multiplication and division ratios.
Section 19 Flash Memory (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values.
Section 19 Flash Memory (g) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses.
Section 19 Flash Memory • • (i) Area-last address (4 bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. SUM (1 byte): Checksum Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses.
Section 19 Flash Memory (k) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command.
Section 19 Flash Memory Error Response H'BF ERROR • Error response, H'BF, (1 byte): Error response to selection of new bit rate • ERROR: (1 byte): Error code H'11: H'24: H'25: H'26: H'27: (5) Sum checking error Bit-rate selection error The rate is not available. Error in input frequency This input frequency is not within the specified range. Multiplication-ratio error The ratio does not match an available ratio. Operating frequency error The frequency is not within the specified range.
Section 19 Flash Memory 4. Bit rate To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is more than 4%, a bit rate error is generated.
Section 19 Flash Memory (6) Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and will enter the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state.
Section 19 Flash Memory (8) Command Order The order for commands in the inquiry selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device-selection (H'10) command. 3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. 4.
Section 19 Flash Memory (9) Programming/Erasing State A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. The programming/erasing commands are listed below. Table 19.
Section 19 Flash Memory • Programming Programming is executed by a programming-selection command and a 128-byte programming command. Firstly, the host should send the programming-selection command and select the programming method and programming MATs. There are two programming selection commands, and selection is according to the area and method for programming. 1. User boot MAT programming selection 2.
Section 19 Flash Memory (a) User boot MAT programming selection The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program. Command • Command, H'42, (1 byte): User boot MAT programming selection Response • H'42 H'06 Response, H'06, (1 byte): Response to user boot MAT programming selection When the programming program has been transferred, the boot program will return ACK.
Section 19 Flash Memory • Command, H'50, (1 byte): 128-byte programming • Programming Address (4 bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e. H'00, H'01, H'00, H'00: H'00010000) • • Programming Data (128 bytes): Data to be programmed The size is specified in the response to the programming unit inquiry.
Section 19 Flash Memory Error Response H'D0 ERROR • Error Response, H'D0, (1 byte): Error response for 128-byte programming • ERROR: (1 byte): Error code H'11: Checksum error H'2A: Address error H'53: Programming error An error has occurred in programming and programming cannot be continued. (10) Erasure Erasure is performed with the erasure selection and block erasure command. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block.
Section 19 Flash Memory (a) Erasure Selection The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program. Command • Command, H'48, (1 byte): Erasure selection Response • H'48 H'06 Response, H'06, (1 byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK.
Section 19 Flash Memory On receiving block number H'FF, the boot program will stop erasure and wait for a selection command. Command • H'58 Size Block number SUM Command, H'58, (1 byte): Erasure • Size, (1 byte): The number of bytes that represents the block number This is fixed to 1.
Section 19 Flash Memory Error Response H'D2 ERROR • Error response: H'D2 (1 byte): Error response to memory read • ERROR: (1 byte): Error code H'11: Sum check error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. (12) User Boot MAT Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user boot MAT, as a 4-byte value.
Section 19 Flash Memory (14) User Boot MAT Blank Check The boot program will check whether or not all user boot MATs are blank and return the result. Command • Command, H'4C, (1 byte): Blank check for user boot MAT Response • H'4C H'06 Response, H'06, (1 byte): Response to the blank check of user boot MAT If all user MATs are blank (H'FF), the boot program will return ACK.
Section 19 Flash Memory (16) Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command • H'4F Command, H'4F, (1 byte): Response H'5F Size Inquiry regarding boot program's state Status ERROR SUM • Response, H'5F, (1 byte): Response to boot program state inquiry • Size (1 byte): The number of bytes. This is fixed to 2.
Section 19 Flash Memory Table 19.
Section 19 Flash Memory 19.9 Usage Notes 1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3.
Section 19 Flash Memory 11. If data other than H'FFFFFFFF is written to the key code area (H'00003C to H'00003F) of flash memory, only H'00 can be read in programmer mode. (In this case, data is read as H'00. Rewrite is possible after erasing the data.) For reading in programmer mode, make sure to write H'FFFFFFFF to the entire key code area.
Section 20 Boundary Scan (JTAG) Section 20 Boundary Scan (JTAG) The JTAG (Joint Test Action Group) is standardized as an international standard, IEEE Standard 1149.1, and is open to the public as IEEE Standard Test Access Port and Boundary-Scan Architecture.
Section 20 Boundary Scan (JTAG) ETCK ETMS TAP controller Decoder ETRST ETDI Shift register SDBSR SDBPR SDIR SDIDR ETDO Mux [Legend] SDIR: SDBPR: SDBSR: SDIDR: Instruction register Bypass register Boundary scan register ID code register Figure 20.1 JTAG Block Diagram Rev. 3.00 Sep.
Section 20 Boundary Scan (JTAG) 20.2 Input/Output Pins Table 20.1 shows the JTAG pin configuration. Table 20.1 Pin Configuration Pin Name Abbreviation I/O Function Test clock ETCK Input Test Clock Input Provides an independent clock supply to the JTAG. As the clock input to the ETCK pin is supplied directly to the JTAG, a clock waveform with a duty cycle close to 50% should be input. For details, see section 24, Electrical Characteristics.
Section 20 Boundary Scan (JTAG) 20.3 Register Descriptions The JTAG has the following registers. • Instruction register (SDIR) • Bypass register (SDBPR) • Boundary scan register (SDBSR) • ID code register (SDIDR) Instructions can be input to the instruction register (SDIR) by serial transfer from the test data input pin (ETDI). Data from SDIR can be output via the test data output pin (ETDO).
Section 20 Boundary Scan (JTAG) 20.3.1 Instruction Register (SDIR) SDIR is a 32-bit register. JTAG instructions can be transferred to SDIR by serial input from the ETDI pin. SDIR can be initialized when the ETRST pin is low or the TAP controller is in the Test-Logic-Reset state, but is not initialized by a reset or in standby mode. Only 4-bit instructions can be transferred to SDIR. If an instruction exceeding 4 bits is input, the last 4 bits of the serial data will be stored in SDIR.
Section 20 Boundary Scan (JTAG) 20.3.2 Bypass Register (SDBPR) SDBPR is a 1-bit shift register. In BYPASS, CLAMP, or HIGHZ mode, SDBPR is connected between the ETDI and ETDO pins. 20.3.3 Boundary Scan Register (SDBSR) SDBSR is a shift register provided on the PAD for controlling the I/O pins of this LSI. Using EXTEST mode or SAMPLE/PRELOAD mode, a boundary scan test conforming to the IEEE1149.1 standard can be performed. Table 20.
Section 20 Boundary Scan (JTAG) Table 20.3 Correspondence between Pins and Boundary Scan Register Pin No. Input/ Pin Name Output Bit No. from ETDI Pin No. Input/ Pin Name Output E04 NMI Input ⎯ ⎯ 195 ⎯ ⎯ Bit No.
Section 20 Boundary Scan (JTAG) Pin No. Input/ Pin Name Output Bit No. Pin No.
Section 20 Boundary Scan (JTAG) Pin No. Input/ Pin Name Output Bit No. Pin No.
Section 20 Boundary Scan (JTAG) Pin No. Input/ Pin Name Output Bit No. Pin No.
Section 20 Boundary Scan (JTAG) Pin No. Input/ Pin Name Output Bit No. Pin No.
Section 20 Boundary Scan (JTAG) 20.3.4 ID Code Register (SDIDR) SDIDR is a 32-bit register. In IDCODE mode, SDIDR can output a fixed code, H'08039447, from the ETDO pin. However, no serial data can be written to SDIDR via the ETDI pin. 31 28 27 0000 1000 Version (4 bits) 12 0000 Rev. 3.00 Sep.
Section 20 Boundary Scan (JTAG) 20.4 Operation 20.4.1 TAP Controller State Transitions Figure 20.2 shows the internal states of the TAP controller. State transitions basically conform to the IEEE1149.1 standard. 1 Test-logic-reset 0 0 1 1 Run-test/idle 1 Select-DR-scan 0 Select-IR-scan 0 1 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Capture-IR 0 0 Shift-IR 1 1 Exit1-IR 0 0 Pause-IR 1 0 1 0 0 Exit2-DR 1 Exit2-IR 1 Update-DR 1 0 Update-IR 1 0 Figure 20.
Section 20 Boundary Scan (JTAG) 20.4.2 JTAG Reset The JTAG can be reset in two ways. • The JTAG is reset when the ETRST pin is held at 0. • When ETRST = 1, the JTAG can be reset by inputting at least five ETCK clock cycles while ETMS = 1. 20.5 Boundary Scan The JTAG pins can be placed in the boundary scan mode stipulated by the IEEE1149.1 standard by setting a command in SDIR. 20.5.1 Supported Instructions This LSI supports the three essential instructions defined in the IEEE1149.
Section 20 Boundary Scan (JTAG) In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin).
Section 20 Boundary Scan (JTAG) (6) IDCODE (Instruction code: B'1110) When the IDCODE instruction is enabled, the value of the ID code register is output from the ETDO pin with LSB first when the TAP controller is in the Shift-DR state. While the IDCODE instruction is being executed, the test circuit does not affect the system circuit. When the TAP controller is in the Test-Logic-Reset state, the instruction register is initialized to the IDCODE instruction. Notes: 1.
Section 20 Boundary Scan (JTAG) 20.6 Usage Notes 1. A reset must always be executed by driving the ETRST pin to 0, regardless of whether or not the JTAG is to be activated. The ETRST pin must be held low for 20 ETCK clock cycles. For details, see section 24, Electrical Characteristics. To activate the JTAG after a reset, drive the ETRST pin to 1 and specify the ETCK, ETMS, and ETDI pins to any value.
Section 20 Boundary Scan (JTAG) 8. If a pin with a pull-up function is sampled while its pull-up function is enabled, 1 can be detected at the corresponding input scan register. In this case, the corresponding enable scan register should be cleared to 0. 9. If a pin with an open-drain function is sampled while its open-drain function is enabled and its corresponding output scan register is 1, 0 can be detected at the corresponding enable scan register.
Section 20 Boundary Scan (JTAG) SDIDR serial data input/output SDIDR is captured into the shift register in Capture-DR in IDCODE mode, and bits 0 to 31 of SDIDR are output in that order from the ETDO pin in Shift-DR. Data input from the ETDI pin is not written to any register in Update-DR. ETDI Shift register Bit 31 . . . . Bit 0 ETDO Bit 31 SDIDR Bit 0 Capture-DR Figure 20.5 Serial Data Input/Output (2) Rev. 3.00 Sep.
Section 20 Boundary Scan (JTAG) Rev. 3.00 Sep.
Section 21 Clock Pulse Generator Section 21 Clock Pulse Generator This LSI incorporates a clock pulse generator which generates the system clock (φ), internal clock, bus master clock, and subclock (φSUB). The clock pulse generator consists of an oscillator, PLL multiplier circuit, system clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and subclock waveform shaping circuit. Figure 21.1 shows a block diagram of the clock pulse generator.
Section 21 Clock Pulse Generator 21.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input. 21.1.1 Connecting Crystal Resonator Figure 21.2 shows a typical method of connecting a crystal resonator. An appropriate damping resistance Rd, given in table 21.1, should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 21.3 shows the equivalent circuit of a crystal resonator.
Section 21 Clock Pulse Generator Table 21.2 Crystal Resonator Parameters Frequency(MHz) 5 6.25 RS (max) (Ω) 100 240 C0 (max) (pF) 7 7 21.1.2 External Clock Input Method Figure 21.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be tied to high in standby mode.
Section 21 Clock Pulse Generator 21.2 PLL Multiplier Circuit The PLL multiplier circuit generates a clock of 4 times the frequency of its input clock. The frequency ranges of the multiplied clock are shown in table 21.5. Table 21.3 Ranges of Multiplied Clock Frequency Crystal Resonator, Input Clock (MHz) Multiplier System Clock (MHz) 5 to 6.25 4 20 to 25 External Clock 21.
Section 21 Clock Pulse Generator 21.7 Clock Select Circuit The clock select circuit selects the system clock that is used in this LSI. A clock generated by the oscillator, to which the EXTAL and XTAL pins are input, and multiplied by the PLL circuit is selected as a system clock when returning from high-speed mode, mediumspeed mode, sleep mode, the reset state, or standby mode. 21.8 Usage Notes 21.8.
Section 21 Clock Pulse Generator 21.8.3 Note on Operation Check This LSI may oscillate at several kHz of frequency even when a crystal resonator is not connected to the EXTAL and XTAL pins or an external clock is not input. Use this LSI after confirming that the LSI operates with appropriate frequency. Rev. 3.00 Sep.
Section 22 Power-Down Modes Section 22 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also seven power-down modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules.
Section 22 Power-Down Modes 22.1 Register Descriptions Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
Section 22 Power-Down Modes Bit Bit Name Initial Value R/W Description 6 STS2 0 R/W Standby Timer Select 2 to 0 5 STS1 0 R/W 4 STS0 0 R/W Select the wait time for clock settling from clock oscillation start when canceling software standby mode. Select a wait time of 8 ms (oscillation settling time) or more, depending on the operating frequency. With an external clock, select a wait time of 500 μs (external clock output settling delay time) or more, depending on the operating frequency.
Section 22 Power-Down Modes Table 22.1 Operating Frequency and Wait Time STS2 STS1 STS0 Wait Time 25M Hz 20 MHz Unit ms 0 0 0 8192 states 0.3 0.4 0 0 1 16384 states 0.7 0.8 0 1 0 32768 states 1.3 1.6 0 1 1 65536 states 2.6 3.3 1 0 0 131072 states 5.2 6.6 1 0 1 262144 states 10.5 13.1 1 1 x Reserved* ⎯ ⎯ Recommended specification Note: * Setting prohibited. [Legend] x: Don't care Rev. 3.00 Sep.
Section 22 Power-Down Modes 22.1.2 Low-Power Control Register (LPWRCR) LPWRCR controls power-down modes. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ 0 R/W Reserved The initial value should not be changed. 5 NESEL 0 R/W Noise Elimination Sampling Frequency Select Selects the frequency by which the subclock (φSUB) input from the EXCL pin is sampled using the clock (φ) generated by the system clock pulse generator.
Section 22 Power-Down Modes 22.1.3 Module Stop Control Registers H, L, and A (MSTPCRH, MSTPCRL, MSTPCRA) MSTPCR specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1.
Section 22 Power-Down Modes • MSTPCRA Initial Value R/W Corresponding Module 7 to 3 MSTPA7 to MSTPA3 All 0 R/W Reserved 2 MSTPA2 0 R/W 14-bit PWM timer (PWMX_1) 1 MSTPA1 0 R/W 14-bit PWM timer (PWMX_0) 0 MSTPA0 0 R/W Reserved Bit Bit Name The initial values should not be changed. The initial value should not be changed.
Section 22 Power-Down Modes 22.1.4 Sub-Chip Module Stop Control Registers BH, BL (SUBMSTPBH, SUBMSTPBL) SUBMSTPB specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. • SUBMSTPBH Bit Bit Name Initial Value 7 to 0 SMSTPB15 All 1 to SMSTPB8 R/W R/W Corresponding Module Reserved The initial values should not be changed.
Section 22 Power-Down Modes 22.2 Mode Transitions and LSI States Figure 22.1 shows the enabled mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The STBY input causes a mode transition from any state to hardware standby mode.
Section 22 Power-Down Modes Table 22.
Section 22 Power-Down Modes 22.3 Medium-Speed Mode The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode when the DTSPEED bit in SBYCR is cleared to 0.
Section 22 Power-Down Modes Medium-speed mode φ, peripheral module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 22.2 Medium-Speed Mode Timing 22.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0. In sleep mode, CPU operation stops but the peripheral modules do not stop. The contents of the CPU’s internal registers are retained.
Section 22 Power-Down Modes 22.5 Software Standby Mode The CPU makes a transition to software standby mode when the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, and the PSS bit in TCSR (WDT_1) cleared to 0. In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all stop.
Section 22 Power-Down Modes Oscillator φ NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 22.3 Software Standby Mode Application Example Rev. 3.00 Sep.
Section 22 Power-Down Modes 22.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low.
Section 22 Power-Down Modes 22.7 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR and SUBMSTP is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cancelled and the module operation resumes at the end of the bus cycle.
Section 22 Power-Down Modes 22.8 Usage Notes 22.8.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, when a high level is output, the current consumption is not reduced by the amount of current to support the high level output. 22.8.2 Current Consumption when Waiting for Oscillation Settling The current consumption increases during oscillation settling. 22.8.
Section 22 Power-Down Modes Rev. 3.00 Sep.
Section 23 List of Registers Section 23 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register Addresses (address order) • Registers are listed from the lower allocation addresses. • The MSB-side address is indicated for 16-bit addresses. • Registers are classified by functional modules. • The access size is indicated. 2.
Section 23 List of Registers Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Host interface control register_4 HICR4 8 H'FD00 LPC 16 2 BT status register 0 BTSR0 8 H'FD02 LPC 16 2 Address BT status register 1 BTSR1 8 H'FD03 LPC 16 2 BT control/status register 0 BTCSR0 8 H'FD04 LPC 16 2 BT control/status register 1 BTCSR1 8 H'FD05 LPC 16 2 BT control register BTCR 8 H'FD06 LPC 16 2 BT interrupt mask register BTIMSR 8
Section 23 List of Registers Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Status register 3 STR3 8 H'FD22 LPC 16 2 SERIRQ control register 4 SIRQCR4 8 H'FD23 LPC 16 2 Address LPC channel 3 address register H LADR3H 8 H'FD24 LPC 16 2 LPC channel 3 address register L LADR3L 8 H'FD25 LPC 16 2 SERIRQ control register 0 SIRQCR0 8 H'FD26 LPC 16 2 SERIRQ control register 1 SIRQCR1 8 H'FD27 LPC 16 2 Input data register 1 I
Section 23 List of Registers Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Noise canceler mode control register P3NCMC 8 H'FE45 PORT 8 2 Noise canceler cycle setting register NCCS 8 H'FE46 PORT 8 2 Port E output data register PEODR 8 H'FE48 PORT 8 2 Port E input data register PEPIN 8 H'FE4A PORT 8 2 Port E data direction register PEDDR 8 H'FE4A PORT 8 2 Port C output data register PCODR 8 H'FE4C PORT 8 2 Port C input
Section 23 List of Registers Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits A/D control register ADCR 8 H'FEB1 ADC 8 2 Noise canceler enable register P4NCE 8 H'FEBA PORT 8 2 Address Noise canceler mode control register P4NCMC 8 H'FEBB PORT 8 2 Port 6 pull-up MOS control register P6PCR 8 H'FEBC PORT 8 2 Port 4 pull-up MOS control register P4PCR 8 H'FEBF PORT 8 2 2 ICCR_3 8 H'FEC0 IIC_3 8 2 2 ICSR_3 8 H'FEC1 IIC_3
Section 23 List of Registers Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Interrupt control register D ICRD 8 H'FEE7 INT 8 2 Interrupt control register A ICRA 8 H'FEE8 INT 8 2 Address Interrupt control register B ICRB 8 H'FEE9 INT 8 2 Interrupt control register C ICRC 8 H'FEEA INT 8 2 IRQ status register ISR 8 H'FEEB INT 8 2 IRQ sense control register H ISCRH 8 H'FEEC INT 8 2 IRQ sense control register L ISCRL 8
Section 23 List of Registers Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Second slave address register_1 SARX_1 8 H'FF8E IIC_1 8 2 I C bus mode register_1 ICMR_1 8 H'FF8F IIC_1 8 2 Slave address register_1 SAR_1 8 H'FF8F IIC_1 8 2 Timer interrupt enable register TIER 8 H'FF90 FRT 8 2 Timer control/status register TCSR 8 H'FF91 FRT 8 2 Free-running counter FRC 16 H'FF92 FRT 16 2 Output Compare register A OCRA 16 H
Section 23 List of Registers Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Port 2 data direction register P2DDR 8 H'FFB1 PORT 8 2 Port 1 data register P1DR 8 H'FFB2 PORT 8 2 Address Port 2 data register P2DR 8 H'FFB3 PORT 8 2 Port 3 data direction register P3DDR 8 H'FFB4 PORT 8 2 Port 4 data direction register P4DDR 8 H'FFB5 PORT 8 2 Port 3 data register P3DR 8 H'FFB6 PORT 8 2 Port 4 data register P4DR 8 H'FFB7 P
Section 23 List of Registers Module Data Bus Width Number of Access States H'FFDE IIC_0 8 2 8 H'FFDE IIC_0 8 2 ICMR_0 8 H'FFDF IIC_0 8 2 SAR_0 8 H'FFDF IIC_0 8 2 Serial mode register_3 SMR_3 8 H'FFE0 SCI_3 8 2 Bit rate register_3 BRR_3 8 H'FFE1 SCI_3 8 2 Serial control register_3 SCR_3 8 H'FFE2 SCI_3 8 2 Transmit data register_3 TDR_3 8 H'FFE3 SCI_3 8 2 Serial status register_3 SSR_3 8 H'FFE4 SCI_3 8 2 Receive data register_3 RDR_3 8 H'FFE5 SCI
Section 23 List of Registers 23.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, so 16-bit registers are shown as 2 lines.
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TWR11 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 LPC TWR12 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TWR13 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TWR14 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TWR15 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IDR3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ODR3 bit 7
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ECS ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ E7 E6 E5 E4 E3 E2 ⎯ ⎯ EVC E1 E0 ECCR EDSB ⎯ ⎯ ⎯ ECSB3 ECSB2 ECSB1 ECSB0 MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 SYSTEM P3NCE P37NCE P36NCE P35NCE P34NCE P33NCE P32NCE P31NCE P30NCE PORT P3NCMC P37NCMC P36NCMC P35NCMC P34NCMC P33NCMC P32NCMC P31NCMC P30NCMC NCCS ⎯ ⎯ ⎯ ⎯ ⎯ NCCK2 NCCK1 NCCK0
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 ADDRE AD9 AD8 AD7 AD6 AD5 AD4 AD1 AD0 ⎯ ⎯ ⎯ ⎯ AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRF ADDRG Bit 3 Bit 2 Bit 1 Bit 0 Module AD3 AD2 ADC ⎯ ⎯ AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADDRH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADCSR ADF ADIE ADST ⎯ ⎯ CH2 CH1 CH0 ADCR TRGS1 TRGS0 SCANE SCANS CKS1 CKS0
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module CRCDOR bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 CRC bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ICXR_0 STOPIM HNDS ICDRF ICDRE ALIE ALSL FNC1 FNC0 IIC_0 ICXR_1 STOPIM HNDS ICDRF ICDRE ALIE ALSL FNC1 FNC0 IIC_1 ICSMBCR SMB5E SMB4E SMB3E SMB2E SMB1E SMB0E FSEL1 FSEL0 IIC ICXR_2 STOPIM HNDS ICDRF ICDRE ALIE ALSL FNC1 FNC0 IIC_2 ICXR_3 S
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SYSTEM MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 ICCR_1 ICE IEIC MST TRS ACKE BBSY IRIC SCP ICSR_1 ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDR_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SARX_1 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX ICMR_1 MLS WAIT CKS2 CKS1
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORT P3PCR P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P2DDR ⎯ ⎯ ⎯ ⎯ P23DDR P22DDR P21DDR P20DDR P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR P2DR ⎯ ⎯ ⎯ ⎯ P23DR P22DR P21DR P20DR P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR P4DDR P47DDR P46
Section 23 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SMR_3* C/A CHR PE O/E STOP MP CKS1 CKS0 SCI_3 (GM) (BLK) (PE) (O/E) (BCP1) (BCP0) (CKS1) (CKS0) BRR_3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCR_3 TIE RIE TE RE MPIE TIE CKE1 CKE0 TDR_3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SSR_3* TDRE RDRF ORER FER PER TEND MPB MPBT (TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT) RDR_3 bi
Section 23 List of Registers 23.
Section 23 List of Registers High-Speed/ Medium- Register Software Hardware Abbreviation Reset WDT Reset Speed Sleep Module Stop Standby Standby Module TWR15 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ LPC IDR3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ODR3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ STR3 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ SIRQCR4 Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized LADR3H Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized LADR3L Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized SIRQCR0 Initialized Initialized
Section 23 List of Registers High-Speed/ Medium- Register Software Hardware Abbreviation Reset WDT Reset Speed Sleep Module Stop Standby Standby NCCS Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized PEODR Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized PEPIN Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized PEDDR Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized PCODR Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized PCPIN Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized PCDDR I
Section 23 List of Registers High-Speed/ Medium- Register Software Hardware Abbreviation Reset WDT Reset Speed Sleep Module Stop Standby Standby Module ICCR_3 Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized IIC_3 ICSR_3 Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized ICDR_3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SARX_3 Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized ICMR_3 Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized SAR_3 Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized ICCR_2 Initializ
Section 23 List of Registers High-Speed/ Medium- Register Software Hardware Abbreviation Reset WDT Reset Speed Sleep Module Stop Standby Standby DTCERC Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized DTCERD Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized DTCERE Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized DTVECR Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized ABRKCR Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized BARA Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized BAR
Section 23 List of Registers High-Speed/ Medium- Register Software Hardware Abbreviation Reset WDT Reset Speed Sleep Module Stop Standby Standby Module DADRA_0 Initialized Initialized ⎯ ⎯ Initialized Initialized Initialized PWMX_0 DACR_0 Initialized Initialized ⎯ ⎯ Initialized Initialized Initialized DADRB_0 Initialized Initialized ⎯ ⎯ Initialized Initialized Initialized DACNT_0 Initialized Initialized ⎯ ⎯ Initialized Initialized Initialized TCSR_0 Initialized
Section 23 List of Registers High-Speed/ Medium- Register Software Hardware Abbreviation Reset WDT Reset Speed Sleep Module Stop Standby Standby Module TCORA_0 Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized TMR_0 TCORA_1 Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized TMR_1 TCORB_0 Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized TMR_0 TCORB_1 Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized TMR_1 TCNT_0 Initialized Initialized ⎯ ⎯ ⎯ ⎯ Initialized TMR_0 TCNT_1 Initi
Section 24 Electrical Characteristics Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings Table 24.1 lists the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage* (pins multiplexed with analog input) VCC –0.3 to +4.3 V Input voltage (pins multiplexed (1) Vin with IIC functions) Input voltage (2) Vin –0.3 to AVCC +0.3 –0.3 to +6.5 Input voltage (except (1), (2) ) Vin –0.3 to VCC +0.
Section 24 Electrical Characteristics 24.2 DC Characteristics Table 24.2 lists the DC characteristics. Table 24.3 lists the permissible output currents. Table 24.4 lists the bus drive characteristics. Table 24.2 DC Characteristics (1) 1 Conditions: VCC = 3.0 V to 3.6 V, AVCC* = 3.0 V to 3.6 V, 1 1 AVref* = 3.0 V to AVCC, VSS = AVSS* = 0 V Symbol Min. Typ. Max. Test Unit Conditions VT– VCC × 0.2 ⎯ ⎯ V VT+ ⎯ ⎯ VCC × 0.7 VT+ - VT– VCC × 0.05 ⎯ ⎯ VT– VCC × 0.3 ⎯ ⎯ VT+ ⎯ ⎯ VCC × 0.
Section 24 Electrical Characteristics Symbol Min. Typ. Max. Test Unit Conditions VIL –0.3 ⎯ VCC × 0.1 V –0.3 ⎯ VCC × 0.2 Port 7 –0.3 ⎯ AVCC × 0.2 SERIRQ, LAD3 to LAD0, LCLK, LRESET, LFRAME –0.3 ⎯ VCC × 0.3 Input pins other than (1) and (3) above –0.3 ⎯ VCC × 0.2 ⎯ ⎯ ⎯ 0.5 ⎯ ⎯ IOH = –200 µA SERIRQ, LAD3 to LAD0 VCC × 0.9 ⎯ ⎯ IOH = –0.5 mA Output pins other than (4) above VCC – 0.5 ⎯ ⎯ IOH = –200 µA VCC – 1.
Section 24 Electrical Characteristics Table 24.2 DC Characteristics (2) 1 Conditions: VCC = 3.0 V to 3.6 V, AVCC* = 3.0 V to 3.6 V, 1 1 AVref* = 3.0 V to AVCC, VSS = AVSS* = 0 V Test Symbol Min. Typ. Max. Unit Conditions Item Input leakage RES, STBY, NMI, FWE, current MD2, MD1 ⏐Iin⏐ ⎯ ⎯ 1.0 ⎯ ⎯ 1.0 VIN = 0.5 to AVCC – 0.5 V ⏐ITSI⏐ ⎯ ⎯ 1.0 VIN = 0.5 to VCC – 0.
Section 24 Electrical Characteristics 3. Pins P80 to P83 and PC0 to PC3 are NMOS push-pull outputs. High levels on pins P80 to P83 and PC0 to PC3 are driven by NMOS. An external pull-up resistor is necessary to provide high-level output from these pins when they are used as an output. 4. Supply current values are for VIH min = VCC – 0.2 V and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 5. When VCC = 3.0 V, VIH min = VCC – 0.2 V, and VIL max = 0.2 V.
Section 24 Electrical Characteristics This LSI 600 Ω HC0 to HC7 LED Figure 24.2 LED Drive Circuit (Example) Rev. 3.00 Sep.
Section 24 Electrical Characteristics 24.3 AC Characteristics Figure 24.3 shows the test conditions for the AC characteristics. 3V RL LSI output pin C C = 30pF : All ports RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level : 0.8 V • High level : 1.5 V RH Figure 24.3 Output Load Circuit 24.3.1 Clock Timing Table 24.4 shows the clock timing.
Section 24 Electrical Characteristics Table 24.5 External Clock Input Conditions Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 25 MHz Item Symbol Min. Max. Unit Test Conditions External clock input low level pulse width tEXL 80 ⎯ ns Figure 24.7 External clock input high level pulse width tEXH 80 ⎯ ns External clock input rising time tEXr ⎯ 5 ns External clock input falling time tEXf ⎯ 5 ns Clock low level pulse width tCL 0.4 0.
Section 24 Electrical Characteristics tcyc tCH tCf φ tCL tCr Figure 24.4 System Clock Timing VCC STBY tOSC1 tOSC1 RES φ Figure 24.5 Oscillation Stabilization Timing φ NMI IRQi ( i = 0 to 15 ) tOSC2 Figure 24.6 Oscillation Stabilization Timing (Exiting Software Standby Mode) Rev. 3.00 Sep.
Section 24 Electrical Characteristics tEXH tEXL VCC × 0.5 EXTAL tEXr tEXf Figure 24.7 External Clock Input Timing VCC 2.7 V STBY VIH EXTAL φ (Internal and external) RES tDEXT* Note: The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW). Figure 24.8 Timing of External Clock Output Stabilization Delay Time Rev. 3.00 Sep.
Section 24 Electrical Characteristics tEXCLH tEXCLL VCC × 0.5 EXCL tEXCLr tEXCLf Figure 24.9 Subclock Input Timing 24.3.2 Control Signal Timing Table 24.7 shows the control signal timing. Only external interrupts NMI and IRQ0 to IRQ15 can be operated based on the subclock (φSUB = 32.768 kHz). Table 24.7 Control Signal Timing Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 25 MHz Item Symbol Min. Max. Unit Test Conditions RES setup time tRESS 200 ⎯ ns Figure 24.
Section 24 Electrical Characteristics φ tRESS tRESS RES tRESW Figure 24.10 Reset Input Timing φ tNMIS tNMIH NMI tNMIW IRQi (i = 0 to 15) tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 24.11 Interrupt Input Timing Rev. 3.00 Sep.
Section 24 Electrical Characteristics 24.3.3 Timing of On-Chip Peripheral Modules Tables 24.8 to 24.11 show the on-chip peripheral module timing. The on-chip peripheral modules that can be operated by the subclock (φSUB = 32.768 kHz) are I/O ports, external interrupts (NMI and IRQ0 to IRQ15), watchdog timer, and 8-bit timer (channels 0 and 1) only. Table 24.8 Timing of On-Chip Peripheral Modules Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 25 MHz Item Symbol Min. Max.
Section 24 Electrical Characteristics T2 T1 φ tPRS tPRH Ports 1 to 8, A, C, and E (read) tPWD Ports 1 to 6, 8, A, C, and E (write) Figure 24.12 I/O Port Input/Output Timing φ tPWOD PWX3 to PWX0 Figure 24.13 PWMX Output Timing tSCKW tSCKr tSCKf SCK1, SCK3 tScyc Figure 24.14 SCK Clock Input Timing SCK1, SCK3 tTXD TxD1, TxD3 (transmit data) tRXS tRXH RxD1, RxD3 (receive data) Figure 24.15 SCI Input/Output Timing (Clock Synchronous Mode) Rev. 3.00 Sep.
Section 24 Electrical Characteristics φ tTRGS ADTRG Figure 24.16 A/D Converter External Trigger Input Timing φ tRESD tRESD RESO tRESOW Figure 24.17 WDT Output Timing (RESO) Rev. 3.00 Sep.
Section 24 Electrical Characteristics 2 Table 24.9 I C Bus Timing Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 25 MHz Item Symbol Min. Typ. Max. Unit Test Conditions SCL input cycle time tSCL 12 ⎯ ⎯ tcyc Figure 24.18 SCL input high pulse width tSCLH 3 ⎯ ⎯ SCL input low pulse width tSCLL 5 ⎯ ⎯ SCL, SDA input rise time tSr ⎯ ⎯ 7.5* SCL, SDA input fall time tSf ⎯ ⎯ 300 SCL, SDA output fall time tOf 20 + 0.
Section 24 Electrical Characteristics SDA0 to SDA3 VIH VIL tBUF tSCLH tSTAH tSP tSTAS tSTOS SCL0 to SCL3 P* S* tSf Sr* tSCLL P* tSr tSDAS tSCL tSDAH Note: * S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Retransmission start condition 2 Figure 24.18 I C Bus Interface Input/Output Timing Table 24.10 LPC Module Timing Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V, φ = 20 MHz to 25 MHz Item Symbol Min. Typ. Max.
Section 24 Electrical Characteristics tLCKH tLcyc LCLK tLCKL LCLK tTXD LAD3 to LAD0, SERIRQ (Transmit signal) tRXS tRXH LAD3 to LAD0, SERIRQ,LFRAME (Receive signal) tOFF LAD3 to LAD0, SERIRQ (Transmit signal) Figure 24.19 LPC Interface (LPC) Timing Rev. 3.00 Sep.
Section 24 Electrical Characteristics Table 24.11 JTAG Timing Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 25 MHz Item Symbol Min. Max. Unit Test Conditions ETCK clock cycle time tTCKcyc 40* 50* ns Figure 24.20 ETCK clock high pulse width tTCKH 15 ⎯ ETCK clock low pulse width tTCKL 15 ⎯ ETCK clock rise time tTCKr ⎯ 5 ETCK clock fall time tTCKf ⎯ 5 ETRST pulse width tTRSTW 20 ⎯ tcyc Figure 24.
Section 24 Electrical Characteristics ETCK tRSTHW RES ETRST tTRSTW Figure 24.21 Reset Hold Timing ETCK tTMSS tTMSH tTDIS tTDIH ETMS ETDI tTDOD ETDO Figure 24.22 JTAG Input/Output Timing Rev. 3.00 Sep.
Section 24 Electrical Characteristics 24.4 A/D Conversion Characteristics Table 24.12 lists the A/D conversion characteristics. Table 24.12 A/D Conversion Characteristics (AN7 to AN0 Input: 80/160-State Conversion) Condition A: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC VSS = AVSS = 0 V, φ = 20 MHz Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 20 MHz to 25 MHz Condition A Item Min. Resolution Typ. Condition B Max. Min.
Section 24 Electrical Characteristics 24.5 Flash Memory Characteristics Table 24.13 and 24.14 lists the flash memory characteristics. Table 24.13 Flash Memory Characteristics (100 Programming/Erasing Cycles Specification) Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Avref = 3.0 V to AVCC, VSS = AVSS =0V Ta = 0°C to +75°C (operating temperature range for programming/erasing) Item Symbol Test Conditions Min. Typ. Max.
Section 24 Electrical Characteristics Table 24.14 Flash Memory Characteristics (1,000 Programming/Erasing Cycles Specification) Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Avref = 3.0 V to AVCC, VSS = AVSS =0V Ta = 0°C to +75°C (operating temperature range for programming/erasing) Item Symbol Test Conditions Min. Typ. Max. Unit ⎯ 1 20 ms/128 bytes ⎯ 40 260 ms/4-Kbyte block ⎯ 300 1500 ms/32-Kbyte block ⎯ 600 3000 ms/64-Kbyte block Σ tP ⎯ 4.
Section 24 Electrical Characteristics 24.6 Usage Notes It is necessary to connect a bypass capacitor between the VCC pin and VSS pin and a capacitor between the VCL pin and VSS pin for stable internal step-down power. An example of connection is shown in figure 24.23. Vcc power supply Bypass capacitor 10 µF VCC External capacitor for internal step-down power stabilization 0.01 µF VSS It is recommended that a bypass capacitor be connected to the VCC pin. (The values are reference values.
Appendix Appendix A. I/O Port States in Each Processing State Table A.
Appendix B. Product Lineup Product Type Type Code Mark Code R4F2153 R4F2153 F2153VBR25KDV PLBG0112GA-A F-ZTAT version Rev. 3.00 Sep.
Appendix Package Dimensions JEITA Package Code P-LFBGA112-10x10-0.80 RENESAS Code PLBG0112GA-A Previous Code BP-112/BP-112V MASS[Typ.] 0.3g D w S B E w S A ×4 v y1 S y A1 A S S ZD e A L K e J Reference Symbol H B G Dimension in Millimeters Min Nom Max D 10.00 F E 10.00 E v D w 0.20 A 1.40 C ZE C. B A1 0.15 0.35 A b 1 2 3 4 5 φ b 6 7 φ 8 9 ×M S A B 10 11 0.40 0.45 0.80 e 0.45 0.50 0.55 x 0.08 y 0.10 y1 0.2 SD SE ZD 1.00 ZE 1.
Appendix Rev. 3.00 Sep.
Main Revisions for This Edition Item Page Revision (See Manual for Details) 3.1 Operating Mode Selection 51 Description amended This MCU supports three operating modes (modes 2, 4, and 6). … Table 3.1 MCU Operating Mode Selection Table amended MCU Operating Mode MD2 MD1 CPU Operating Mode Description 2 1 1 Advanced Extended mode with on-chip ROM 4 0 0 — Flash programming/erasing 6 0 1 Emulation On-chip emulation mode Single-chip mode 5.
Item Page 7.2.5 DTC Transfer 102 Count Register A (CRA) Revision (See Manual for Details) Description amended … It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. The number of times data is transferred is one when the setting value of CRA is H'0001, 65,535 when the setting value is H'FFFF, and 65,536 when the setting value is H'0000.
Item Page Revision (See Manual for Details) 15.4.4 Master Receive Operation 368 Figure amended SCL is fixed low until ICDR is read Figure 15.
Item Page 24.2 DC Characteristics 674 Table 24.2 DC Characteristics (1) Revision (See Manual for Details) Table amended Item Schmitt trigger input voltage DB7 to DB4, ExDB7 to ExDB0, (1) EVENT7 to EVENT0, (Ex)IRQ15, (Ex)IRQ14, ExIRQ13, ExIRQ12, (Ex)IRQ11, (Ex)IRQ10, ExIRQ9, ExIRQ8, (Ex)IRQ7 to (Ex)IRQ0, ETRST, XTAL, EXCL, ADTRG SCL3 to SCL0, SDA3 to SDA0 RES, STBY, NMI, FWE, MD2, Input MD1 high voltage EXTAL 24.5 Flash Memory Characteristics 694 Table 24.
Index Numerics C 14-bit PWM timer (PWMX)................... 177 16-bit count mode................................... 227 16-bit free-running timer (FRT) ............. 193 8-bit timer (TMR)................................... 211 Cascaded connection............................... 227 Chain transfer.......................................... 116 Clock pulse generator ............................. 625 Clocked synchronous mode .................... 289 CMIA......................................................
Effective address extension ...................... 40 ERI1........................................................ 310 ERI2........................................................ 310 Error protection ...................................... 571 Exception handling ................................... 57 Exception handling vector table ............... 58 Extended control register (EXR) .............. 23 External clock ......................................... 627 F Flash MAT configuration .....................
O OCIA ...................................................... 204 OCIB ...................................................... 204 On-board programming .......................... 538 On-board programming mode ................ 509 Operating modes....................................... 51 Operation field.......................................... 40 Output compare ...................................... 201 Overflow................................................. 242 Overrun error ..............................
HISEL................................................. 445 ICCR........................................... 340, 656 ICDR........................................... 331, 657 ICMR.......................................... 335, 657 ICRA............................................. 68, 654 ICRB............................................. 68, 654 ICRC............................................. 68, 654 ICRD............................................. 68, 654 ICSMBCR ..................................
SDBPR ............................................... 610 SDBSR ............................................... 610 SDIDR ................................................ 616 SDIR ................................................... 609 SERIRQ .............................................. 476 SIRQCR...................................... 434, 651 SMICCSR........................................... 447 SMICDTR .......................................... 447 SMICFLG...........................................
W Watchdog timer (WDT).......................... 235 Rev. 3.00 Sep. 28, 2009 Page 710 of 710 REJ09B0384-0300 Watchdog timer mode............................. 242 WOVI .....................................................
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2153 Group Publication Date: Rev.1.00, March 17, 2008 Rev.3.00, September 28, 2009 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2009. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8S/2153 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0384-0300
