Datasheet

REJ09B0465-0300 Rev. 3.00 Page 973 of 982
Sep 17, 2010
Item Page Revision (See Manual for Details)
21.2 Register Descriptions
21.2.3 I
2
C Bus Control
Register 2 (ICCR2)
735,
736
Added
Bit Symbol Description
7 BBSY*
1
*
3
This bit enables to confirm whether the I
2
C
bus is…
6 SCP*
3
The SCP bit controls the issue of
start/stop…
5 SDAO*
3
This bit is used with SDAOP (bit 4) when
modifying output level of SDA. This bit
should not be manipulated during transfer.
Writing 1 to the IICRST bit also sets this bit
to 1.
:
3 SCLO This bit monitors SCL output level. When
reading and SCLO is 1, SCL pin outputs
high. When reading and SCLO is 0, SCL pin
outputs low. Writing 1 to the IICRST bit also
sets this bit to 1.
Notes: 1. In standby mode, the BBSY bit in ICCR2 is
reset.
2. Clear IICRST to 0 by software since this bit is
not cleared automatically.
3. Writing to this bit is invalid during a reset due to
setting the IICRST bit in ICCR2 to 1.
21.2.6 I
2
C Bus Status
Register (ICSR)
741 Added
Bit
Description
7
[Setting conditions]
:
• When 1 is written to IICRST in ICCR2 in
master transmit mode and slave transmit
mode
21.6 Usage Notes
21.6.3 Note regarding Master
Receive Mode of I
2
C-Bus
Interface Mode
765 Added