Datasheet

REJ09B0465-0300 Rev. 3.00 Page 971 of 982
Sep 17, 2010
Item Page Revision (See Manual for Details)
20.2 Register Descriptions 682 Amended
Channel 2
• Receive shift register_2 (RSR_2)
• Receive data register_2 (RDR_2)
• Transmit shift register_2 (TSR_2)
• Transmit data register_2 (TDR_2)
• Serial mode register_2 (SMR_2)
• Serial control register_2 (SCR3_2)
• Serial status register_2 (SSR_2)
• Bit rate register_2 (BRR_2)
• Sampling mode register_2 (SPMR_2)
• IrDA control register_2 (IrCR_2)
Channel 3
• Receive shift register_3 (RSR_3)
• Receive data register_3 (RDR_3)
• Transmit shift register_3 (TSR_3)
• Transmit data register_3 (TDR_3)
• Serial mode register_3 (SMR_3)
• Serial control register_3 (SCR3_3)
• Serial status register_3 (SSR_3)
• Bit rate register_3 (BRR_3)
• Sampling mode register_3 (SPMR_3)
20.6.1 Transmission 721 Amended
… The high-level pulse can be selected using the IrCKS
2
to IrCKS
0 bits in IrCR.
20.6.3 High-Level Pulse
Width Selection
722 Amended
Table 20.7 shows possible settings for bits IrCKS
2 to
IrCKS
0 (minimum pulse width), and this LSI's operating
frequencies and bit rates, …
Table 20.7 Settings of Bits
IrCKS
2 to IrCKS0
722 Table title amended