Datasheet

REJ09B0465-0300 Rev. 3.00 Page 969 of 982
Sep 17, 2010
Item Page Revision (See Manual for Details)
17.4 Operation of Output
Compare Mode
623 Amended
Writing 0 to the RCS3 bit in TRECSR sets the timer RE in
output compare mode and causes it to operate as a
counter provided with an 8-bit compare match function.
Four count sources can be selected. When used in output
compare mode, the timer RE should be initialized in
reference to figure 17.3. When timer RE is initialized, first
select the output-compare mode through the RCS3 bit in
TRECSR and then perform the initial setting procedure
shown in figure 17.3.
Section 18 Timer RG
18.3 Operation
• TGIOA pin
• TGIOB pin
643,
644
Tables amended
18.3.1 Timer Mode
Figure 18.2 Example of
Setting Procedure for
Waveform Output by
Compare Match
645 Replaced
Figure 18.8 Input Capture
Input Signal Timing
650 Replaced
18.3.2 PWM Mode
Figure 18.9 Example of PWM
Mode Setting Procedure
651 Replaced
18.3.3 Phase Counting Mode
Figure 18.17 Phase
Difference, Overlap, and
Pulse Width in Phase
Counting Mode
660 Amended
Pulse width: 3 states or more
660 Amended
Buffer operation differs according to whether GR has been
designated as an output compare register or an input
capture register.
Table 18.10 shows the register combinations used in buffer
operation.
18.3.4 Buffer Operation
661 Amended
(2) When GR is an input capture register