Datasheet

Page 964 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
Item Page Revision (See Manual for Details)
11.8 Usage Notes
11.8.4 Limitation on Usage of
the Interrupt Vector Offset
Register (VOFR)
368 Added
Section 12 Event Link
Controller
12.1 Overview
Figure 12.1 Block Diagram of
Event Link Controller
370 Amended
ELCR
ELSR0 to ELSR32
12.2 Register Descriptions
12.2.2 Event Link Setting
Registers 0 to 32 (ELSR0 to
ELSR32)
372 Amended
… Table 12.1 shows the correspondence between ELSR0
to ELSR32 and the peripheral modules. …
12.2.7 Port-Group Control
Registers 1 and 2 (PGC1 and
PGC2)
379 Amended
…
The correspondence between PGC and ports is shown in
table 12.3.
12.2.8 Port Buffer Registers 1
and 2 (PDBF1 and PDBF2)
380 Amended
PDBF is an 8-bit readable/writable register used in
combination with PGR. For PDBF operations, see section
12.3, Operation. The correspondence of PDBF and PDR is
shown in table 12.3.
12.3 Operation
12.3.5 Port Operation upon
Event Input and Event
Generation
392 Amended
(1) Single-Ports and Port-Groups
… A port-group can be set by specifying any two or
more bits in the port* to which an event can be
connected using the PGC register. …