Datasheet

Section 3 Exception Handling
REJ09B0465-0300 Rev. 3.00 Page 73 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Table 3.4 Status of CCR and EXR after Trap Instruction Exception Handling
CCR EXR
Interrupt Control Mode I UI I2 to I0 T
0 1 ⎯ ⎯ ⎯
2 1 ⎯ ⎯ 0
[Legend]
1: Set to 1
0: Cleared to 0
⎯: Retains value prior to execution.
3.7 Stack Status after Exception Handling
Figure 3.2 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
CCR
PC (24 bits)
SP
EXR
Reserved
*
CCR
PC (24 bits)
SP
Advanced Modes
Interrupt control mode 0 Interrupt control mode 2
Note: * Ignored on return.
Figure 3.2 Stack Status after Exception Handling