Datasheet

REJ09B0465-0300 Rev. 3.00 Page 963 of 982
Sep 17, 2010
Item Page Revision (See Manual for Details)
10.8.11 Port Data Register A
(PDRA)
324 Amended
PDRA is a register that stores output data for port A pins.
When PCRA bits are set to 1, the values stored in PDRA
are output.
…
When the pins are set as analog input channels by ADCSR
and ADCR of the A/D converter, however, the
corresponding PDRA bits are always read as 1 even if the
respective PCRA bits are cleared to 0.
10.9 Port B
10.9.2 Port Data Register B
(PDRB)
328 Added and amended
PDRB is a register that stores output data for port B pins.
When PCRB bits are set to 1, the values stored in PDRB
are output.
When PDRB is read while PCRB bits are set to 1, the
values stored in PDRB are read. If PDRB is read while
PCRB bits are cleared to 0, the pin states are read
regardless of the value stored in PDRB.
When the pins are set as analog input channels by ADCSR
and ADCR of the A/D converter, however, the
corresponding PDRB bits are always read as 1 even if the
respective PCRB bits are cleared to 0.
…
Section 11 Data Transfer
Controller (DTC)
11.4 Location of Register
Information and DTC Vector
Table
348 Amended
The configuration of the vector address is a 2-byte unit.
These two bytes specify the lower bits of the start address.
Whenever the DTC is used, set the VOFR to H'0000 (its
default value).
Table 11.3 Interrupt Sources,
DTC Vector Addresses, and
Corresponding DTCEs
350 Amended
Origin of
Activation
Source Activation Source Vector Address*
1
A/D converter
unit 2*
2
IADEND_2
(conversion completion)
H'440 to H'441
IADCMP_2
(compare condition match)
H'442 to H'443