Datasheet

REJ09B0465-0300 Rev. 3.00 Page 957 of 982
Sep 17, 2010
Item Page Revision (See Manual for Details)
Section 4 Interrupt Controller
4.2 Register Descriptions
4.2.1 Interrupt Control
Register (INTCR)
78 Deleted
Bit
Description
2 0: AD1 or AD2 conversion is started at falling
edge of ADTRG2 input.
1: AD1 or
AD2 conversion is started at rising
edge of ADTRG2 input.
4.2.5 IRQ Status Register
(ISR)
85 Description amended
[Setting condition]
• When the interrupt edge selected by ISCR occurs.
4.2.7 Interrupt Vector Offset
Register (VOFR)
87 Note added
Section 5 Clock Pulse
Generator
5.2 Register Descriptions
5.2.5 Power-Down Control
Register 3 (LPCR3)
119,
120
Amended
Bit
Symbol R/W
5 STBYINT R
4 SLEEPINT R
Section 6 Power-Down
Modes
141 Deleted
• Standby Mode
The CPU and all the on-chip peripheral modules are
stopped. However, timer RE (TMRE)
can operate when
the realtime clock mode is selected. The watchdog
timer (WDT) also operates when the low-speed OCO or
subclock φsub is selected as the WDT clock source.
Section 7 ROM
7.3 CPU Reprogramming
Mode
7.3.2 EW1 Mode
161 Amended
… If erasure has not been completed at the end of interrupt
processing (FMERSF = 1 in FLMSTR), resume erasure by
setting the FMSPREQ bit to 0.