Datasheet

Section 3 Exception Handling
REJ09B0465-0300 Rev. 3.00 Page 69 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
3.3.2 Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, VOFR is cleared to H'0000, the T bit in EXR is cleared to 0, and the I bit in EXR
and CCR is set to 1.
2. The low-speed on-chip oscillator is selected as a system clock.
3. After the reset exception handling vector address is read and transferred to the PC, program
execution starts from the address indicated by the PC.
Figure 3.1 shows an example of the reset sequence.
φ
RES
Internal
address bus
Internal
read signal
Internal
write signal
Internal
data bus
Vector fetch
(1) (3) (5)
High
Internal
processing
(2) (4) (6)
(1) (3)
(2) (4)
(5)
(6)
:Reset exeption handling vector address (when reset, (1) = H'000000, (3) = H'000002)
:Start address (contents of reset exception handling vector address)
:Start address ((5) = (2)(4))
:First program instruction
Prefetch of first
program instruction
Figure 3.1 Reset Sequence