Datasheet

Section 3 Exception Handling
Page 68 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(2) Reset Control Register (RSTCR)
b7
WI
1
b6
WE
0
b5
⎯
0
b4
⎯
0
b3
⎯
0
b2
⎯
0
b1
⎯
0
b0
SRST
0
H'FF06DA
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 WI Write inhibit 0: Writing is permitted.
1: Writing is inhibited.
W
6 WE Write enable 0: Writing is disabled.
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE.
[Clearing condition]
When 0 is written to WI and WE.
R/W
5 to 1 ⎯ Reserved These bits are read as 0. The write value should
be 0.
⎯
0 SRST Software reset 0: Normal operation
1: A software reset is generated.
R/W
Note: A MOV instruction should be used to write to this register.
• WI bit (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
• WE bit (write enable)
Bit 0 in this register can be written to when this bit is 1.
• SRST bit (software reset)
A software reset is generated when this bit is 1.