Datasheet

Section 3 Exception Handling
REJ09B0465-0300 Rev. 3.00 Page 67 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(1) Reset Source Flag Register (RSTFR)
b7
⎯
0
b6
⎯
0
b5
SWRST
(0)
b4
PRST
(0)
b3
LVD2RST
(0)
b2
LVD1RST
(0)
b1
PORRST
(0)
b0
WRST
(0)
H'FF0620
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 ⎯
6 ⎯
Reserved This bit is read as 0. The write value should be 0. ⎯
5 SWRST Software reset
detection flag
1: Indicates that a reset by a software reset occurs.
0: Indicates that a reset by a software reset does
not occur.
R/W
4 PRST RES pin reset
detection flag
1: Indicates that a reset by a RES pin reset occurs.
0: Indicates that a reset by a RES pin reset does
not occur.
R/W
3 LVD2RST LVD2 reset
detection flag
1: Indicates that a reset by an LVD2 reset occurs.
0: Indicates that a reset by an LVD2 reset does not
occur.
R/W
2 LVD1RST LVD1 reset
detection flag
1: Indicates that a reset by an LVD1 reset occurs.
0: Indicates that a reset by an LVD1 reset does not
occur.
R/W
1 PORRST LVD0 reset
detection flag
1: Indicates that a reset by an LVD0 reset occurs.
0: Indicates that a reset by an LVD0 reset does not
occur.
R/W
0 WRST Watchdog timer
reset detection
flag
1: Indicates that a reset by a watchdog timer
overflows.
0: Indicates that a reset by a watchdog timer does
not occur.
R/W
Note: Each flag in this register can be cleared by writing 0 to it. The write value to the reserved
bits should always be 0.