Datasheet

Section 26 Low-Voltage Detection Circuits

REJ09B0465-0300 Rev. 3.00 Page 879 of 982

Sep 17, 2010

H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group

(5) Low Voltage Detect Reset 0 (LVDR0)

LVDR0 is a reset generated by the LVD0 circuit. Figure 26.14 shows the operation timing of the

LVDR0.

After a power-on reset is released, the LVD0 circuit is always enabled.

When the power-supply voltage falls below Vdet0, the LVDR0 clears the LVDRES0 signal to 0,

and resets the prescaler, and a power-on reset operation is enabled. When the power-supply

voltage rises above the Vdet0 voltage again, the prescaler starts counting. It counts 128 φloco

cycles, and then releases the internal reset signal.

Note that if the power supply voltage falls below V

LVD0min

= 1.8 V and then rises from that point, the

LVDR0 may not occur. Such a case should be evaluated thoroughly.

LVDRES0

LVD0min

Vdet0

GND

OVF

Prescaler

reset signal

Internal

reset signal

128 φloco cycles

Prescaler

counter starts

Reset released

Figure 26.14 Operation Timing of LVDR0