Datasheet

Section 26 Low-Voltage Detection Circuits
REJ09B0465-0300 Rev. 3.00 Page 869 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
26.3.2 Low-Voltage Detection Circuit
(1) Low Voltage Detect Reset 2 (LVDR2)
LVDR2 is a reset generated by the LVD2 circuit. Figure 26.6 shows the operation timing of the
LVDR2.
The LVD2 enters the module-standby state after release from a power-on reset. To operate the
LVDR2, set the VD2E bit in LD2CRL to 1, wait for 50 μs (t
d(E-A)
) until the detection voltage and
the low-voltage detection circuit 2 operation have stabilized using a software timer, etc., then set
the VD2MS and VD2RE bits in LD2CRH to 1. After that, the output settings of I/O ports must be
made. To cancel the LVDR2, first the VD2RE bit in LD2CRH should be cleared to 0 and then the
VD2E bit in LD2CRL should be cleared to 0. Figure 26.7 shows the procedure to set the LVDR2.
When the power-supply voltage falls below Vdet2, the LVDR2 clears the LVDRES2 signal to 0,
and resets the prescaler. The low-voltage detection reset state remains in place until a power-on
reset is generated. When the power-supply voltage rises above the Vdet2 voltage again, the
prescaler starts counting. It counts 32 φloco cycles, and then releases the internal reset signal.
Note that if the power supply voltage falls below V
LVD2min
= 2.7 V and then rises from that point, the
LVDR2 may not occur. Such a case should be evaluated thoroughly.
If the power supply voltage falls below Vdet0, a power-on reset occurs.
LVDRES2
V
CC
Vdet2
Vdet0
GND
OVF
Prescaler
reset signal
Internal
reset signal
32 φloco cycles
Prescaler
counter starts
Reset released
Figure 26.6 Operation Timing of LVDR2