Datasheet

Section 2 CPU
REJ09B0465-0300 Rev. 3.00 Page 63 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
2.9 Usage Notes
2.9.1 TAS Instruction
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The H8S
and H8/300 Series C/C++ Compiler of Renesas Electronics Corp. does not generate a TAS
instruction. Accordingly, when a TAS instruction is used as a user-defined embedded function,
register ER0, ER1, ER4, or ER5 should be used.
2.9.2 STM and LDM Instructions
The ER7 register is used as a stack pointer in an STM and LDM instructions. Accordingly, ER7
cannot be stored by STM or loaded by LDM. Two, three, or four registers can be stored or loaded
by a single STM or LDM instruction. The combination of registers that can be stored or loaded are
as follows.
• Two registers: ER0 and ER1, ER2 and ER3, or ER4 and ER5
• Three registers: ER0 to ER2 or ER4 to ER6
• Four registers: ER0 to ER3
The H8S and H8/300 Series C/C++ Compiler of Renesas Electronics Corp. does not generate an
STM or LDM instruction that uses ER7.
2.9.3 Note on Bit Manipulation Instructions
Bit manipulation instructions such as BSET, BCLR, BNOT, BST, and BIST read data in byte
units, perform bit manipulation, and write data in byte units. Thus, care must be taken when these
bit manipulation instructions are executed for a register or port including write-only bits.
In addition, the BCLR instruction can be used to clear the flag of an internal I/O register. In this
case, if the flag to be cleared has been set by an interrupt processing routine, the flag need not be
read before executing the BCLR instruction.