Datasheet

Section 2 CPU
Page 62 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
2. If the CPU is in sleep mode at the time of the request, bus mastership is transferred
immediately.
Exception
handling state
Program execution state
Bus-released state
Reset state
*
SLEEP instruction
Program stop state
End of bus request
Bus request
Request for exception handling
Reset request
End of exception handling
Note: * A transition to the reset state occurs in any of the following cases.
1. When RES goes low in any state
2. When the watchdog timer overflows
3. When an LVD reset is caused by a low-voltage detection
Request for
exception handling
Reset requ
est
Reset release
Reset req
uest
Bus r
eq
uest
End of b
us request
Reset request
Figure 2.11 State Transitions