Datasheet

Section 2 CPU
REJ09B0465-0300 Rev. 3.00 Page 61 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
2.8 Processing States
The H8S/2000 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.11 indicates the state
transitions.
• Reset state
In this state the CPU and internal peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. For details, see section 3, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
• Exception-handling state
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, see section 3, Exception Handling.
• Program execution state
In this state the CPU executes program instructions in sequence.
• Bus-released state
The bus-released state occurs when the bus has been released in response to a bus request*
from a bus master (DTC) other than the CPU. While the bus is released, the CPU halts
operations.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed. For details, see section 6, Power-Down Modes.
Notes: * The DTC requests bus mastership when an activation request for the DTC is generated.
Bus mastership is transferred from the CPU to the DTC with the following timing.
1. Bus mastership is transferred at the end of the current bus cycle.
However, when the bus activity for a single instruction is divided up into multiple bus
cycles due to longword access, etc., the bus mastership will not necessarily be
transferred at the end of the current bus cycle. For details, see section 2.7, Bus States
During Instruction Execution, in the H8S/2600 Series, H8S/2000 Series Software
Manual.