Datasheet

Section 24 A/D Converter
REJ09B0465-0300 Rev. 3.00 Page 839 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
AN0
VAL[9:0]
CMP0 in CMPR
ADST
ADF
Comparison voltage input
Specified voltage
Wait for comparison
AN1
Comparison voltage input Wait for comparison Wait for comparison
Previous comparison result Comparison result
CMP1 in CMPR
Previous comparison result
Comparison result
Figure 24.6 A/D Converter Operation in Compare Mode
(When AN0 to AN2 Channels are Selected in Scan Mode)
24.5.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when A/D conversion start delay time (t
D
) passes after the ADST bit is set to 1, then starts
conversion. Figure 24.7 shows the A/D conversion timing. Table 24.6 indicates the A/D
conversion time.
As indicated in figure 24.7, the A/D conversion time (t
CONV
) includes t
D
and the input sampling time
(t
SPL
). The length of t
D
varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in tables 24.6.
In scan mode, the values given in table 24.6 apply to the first conversion time. The values given in
table 24.7 apply to the second and subsequent conversions. In any conversions, the CKS[1:0] bits
in ADCR should be set so that the conversion time should fall within the specified A/D conversion
characteristics range.