Datasheet

Section 24 A/D Converter
Page 838 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
24.5.2 Scan Mode in Comparison Mode
In scan mode in comparison mode, the analog input of the selected channels (four or eight
maximum) are compared sequentially with the specified voltage. Operations are as follows.
1. When the ADST bit in ADCSR is set to 1 by a software, timer RC, timer RD or external
trigger input, comparison between the analog input of the selected channels and the voltage
specified by the VAL[9:0] bits is started.
The comparison on maximum four channels (SCANE = 1 and SCANS= 0) or on maximum
eight channels (SCANE = 1 and SCANS= 1) can be selected. When the consecutive
comparison is performed on the four channels, the comparison starts on AN0 when CH3 = 0
and CH2 = 0, AN4 when CH3 = 0 and CH2 = 1, or AN8 when CH3 = 1 and CH2 = 0. When
the consecutive comparison is performed on the eight channels, the comparison starts on AN0
when CH3 = 0 and CH2 = 0.
2. When comparison for each channel is completed, the result is sequentially transferred to a bit
corresponding to each channel.
3. When comparison of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. In addition, if a condition
specified by the CMPFC1 or CMPFC0 bits is satisfied in any of the selected channels, the
CMPF bit in CMPCSR is set to 1. If the CMPIE bit is set to 1 at this time, a CMPI interrupt is
requested. The A/D converter starts comparison from the first channel of the channel set.
4. The ADST bit is not cleared automatically when ADSTCLR = 0, and steps [2] to [3] are
repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0 during
comparison, the A/D converter stops operation and enters wait state. If the ADST bit is later
set to 1, the A/D converter starts comparison from the first channel of the channel set.