Datasheet

Section 24 A/D Converter
Page 828 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
24.2.6 Compare Control/Status Register (CMPCSR)
Address:
Bit:
Value after reset:
b7
CMPF
0
b6
CMPIE
0
b5
CMPFC1
0
b4
CMPFC0
0
b3
⎯
0
b2
⎯
0
b1
⎯
0
b0
⎯
0
H'FF05E2, H'FF0602
Bit Symbol Bit Name Description R/W
7 CMPF CMPI interrupt
status
[Setting condition]
If the condition specified by the CMPFC1 or CMPFC0
bit is satisfied when comparison has been completed.
[Clearing conditions]
• When the A/D converter operating mode is
changed from A/D conversion mode to compare
mode according to the ADM bit in ADMR setting.
• When 0 is written to this bit after this bit is read as
1.
• When the DTC is activated by a CMPI interrupt
and the DISEL bit in MRB of the DTC is 0.
• When this LSI enters standby mode or module
standby mode.
R/W
6 CMPIE CMPI interrupt
enable
0: Disables a compare match interrupt (CMPI).
1: Enables a compare match interrupt (CMPI).
R/W