Datasheet

Section 24 A/D Converter
REJ09B0465-0300 Rev. 3.00 Page 825 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
24.2.4 A/D Mode Register (ADMR)
Address:
Bit:
Value after reset:
b7
⎯
0
b6
⎯
0
b5
ADM1
0
b4
⎯
0
b3
⎯
0
b2
⎯
0
b1
⎯
0
b0
⎯
0
H'FF05F4, H'FF0614
Bit Symbol Bit Name Description R/W
7, 6 ⎯ Reserved These bits are read as 0. The write value should
be 0.
⎯
5 ADM1 A/D converter
operating mode
selection
0: A/D conversion mode
1: Compare mode
R/W
4 to 0 ⎯ All 0 These bits are read as 0. The write value should
be 0.
⎯
Note: The A/D converter operating mode should be changed while the ADST bit in ADCSR is 0.
• ADM1 bit (A/D conversion mode selection)
If the A/D converter operating mode changes from conversion mode to compare mode, CMPR,
CMPCSR, and CMPVAL are initialized to H'00.